Sense Amplifier Write Booster for Dual Rail Memory
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Solution Overview
Problem
Writing into memory cells with a large dual rail voltage supply differential is challenging due to failed operations and slow write speeds, as the memory periphery circuitry, operating at a low voltage, cannot sufficiently drive bit line voltages to change data states, and increasing write drivers would require larger circuitry and higher power consumption.
Innovation Solution
A sense amplifier is coupled to the bit lines during write operations, pre-charged to the periphery supply voltage and grounded, to improve the drive of write data voltages, enhancing reliability and speed without increasing the strength of existing write drivers or adding significant circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the memory periphery circuitry operates at a low voltage to minimize power consumption, then power consumption is reduced, but write operations fail or become slow because the periphery circuitry cannot sufficiently drive the bit line voltages
Solution Approach 1:
A sense amplifier is introduced as an intermediary component between the low-voltage periphery circuitry and the memory array. The sense amplifier receives weak drive signals from the periphery circuitry and amplifies them to sufficient voltage levels to reliably drive the bit lines and change the state of memory cells, thereby enabling reliable write operations while maintaining low power consumption in the periphery circuitry
2Reliability
If larger write drivers are provided in the memory periphery circuitry to eliminate failed write operations and speed up write operations, then write reliability and speed are improved, but circuit layout area and power consumption increase
Solution Approach 1:
The write driver function is segmented into two separate components: a compact periphery write driver that generates initial write signals, and a sense amplifier that provides the additional drive strength needed. This segmentation allows the periphery circuitry to remain small while still achieving reliable and fast write operations through the combined action of both components
Data Source
AI summary
A memory includes a memory cell that operates in response to an array supply voltage, and a corresponding pair of bit lines that are pre-charged to a periphery supply voltage prior to each access of the memory cell. A sense amplifier coupled to the bit lines operates in response to the periphery supply voltage. The periphery supply voltage is less than the array supply voltage to enable power savings within the memory. A first pair of transistors is configured to couple the sense amplifier to the bit lines during write accesses to the memory cell, thereby boosting the write voltages applied to the bit lines during a write operation. That is, the first pair of transistors is configured such that the sense amplifier pulls one of the bit lines toward the periphery supply voltage (and the other one of the bit lines toward the ground supply voltage) during write accesses.