Row Address Control Circuit Power Reduction
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Solution Overview
Problem
Conventional semiconductor integrated circuits experience high current consumption due to continuous generation of local row enable signals in refresh mode, leading to inefficiency and power loss, especially since each memory bank has a dedicated row address control circuit.
Innovation Solution
A row address control circuit that generates a refresh combination signal with a ground-level electric potential in refresh mode, allowing the row address control units to convert global row enable signals into local row enable signals only when necessary, thereby reducing unnecessary current flow and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the row address control circuit continuously generates local row enable signals in refresh mode, then the memory banks can be activated for refresh operations, but current consumption increases significantly
Solution Approach 1:
The patent applies periodic action by controlling the row address control circuit to operate only during necessary periods (normal operation mode) and remain inactive during refresh mode. The circuit generates local row enable signals periodically when bank active signals are asserted, rather than continuously, thereby reducing current consumption while maintaining refresh operation capability through alternative refresh control mechanisms.
Solution Approach 2:
The patent implements dynamics by making the row address control circuit's operation state variable - it can be dynamically enabled or disabled based on the operational mode. The circuit responds dynamically to bank active signals and global row enable signals, activating only when needed for normal data operations and remaining inactive during refresh operations, thus adapting its energy consumption to actual operational requirements.
2Adaptability or versatility
If the row address control circuit is provided for each memory bank to enable independent control, then the memory banks can be selectively activated, but the number of control circuits increases leading to higher overall power loss
Solution Approach 1:
The patent applies the taking out principle by extracting the continuous signal generation function from the row address control circuit during refresh mode. The circuit maintains its bank-specific control capability but removes the unnecessary continuous operation component, keeping only the essential bank selection and signal conversion functions active when needed, thereby reducing overall power loss while preserving selective bank activation capability.
3Measurement precision
If the bank active pulse signal has a shorter enable time than the bank active signal, then the control precision is improved, but the circuit operates at high electric potential for longer periods increasing power consumption
Solution Approach 1:
The patent applies preliminary anti-action by anticipating the power consumption issue caused by prolonged high electric potential and implementing a disable mechanism. The row address control circuit is designed to be disabled during refresh mode before the prolonged high potential period begins, preventing the power consumption problem from occurring in the first place, while still maintaining precise enable timing control during normal operation when the circuit is active.
Data Source
AI summary
Disclosed are a row addresses control circuit of a semiconductor integrated circuit and method of controlling row addresses using the same. The circuit includes: a pulse generator receiving a bank active signal to generate a bank active pulse signal; a refresh mode input circuit combining the bank active pulse signal with a refresh signal to generate a refresh combination signal; and a plurality of row address control units driving and latching each global row enable signal to convert the global row enable signal to a local row enable signal in response to an input of the refresh combination signal.