Memory Page Latch Read Mode for NV Write Verification
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Solution Overview
Problem
Current non-volatile memory systems require additional silicon area and complex control logic for data verification, and the process of checking page latch functionality is time-consuming due to long high voltage write cycles.
Innovation Solution
The method involves reading memory cell data in normal mode and comparing it directly with page latch data to verify successful write/read operations without writing to memory cells, using page latch read mode for Design for Test and optimizing high voltage parameters for best reliability, allowing for rapid page latch functionality checks without long high voltage cycles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external shadow memory, flip flops, and databus elements are used to store and transfer page latch data for verification, then data write verification capability is improved, but silicon area and device complexity increase
Solution Approach 1:
The page latch circuit is designed to perform multiple functions: it serves as both the data buffer during write operations and as a verification storage element. The same page latch that holds data during programming also provides the reference data for verification by comparing its contents with the shadow memory or external storage, eliminating the need for separate verification-specific circuitry.
Solution Approach 2:
The patent creates a copy of the page latch data in shadow memory or external storage during the write operation. This copy is then used for verification purposes by comparing it with the original page latch contents after the write operation completes, enabling verification without requiring additional dedicated verification storage during the write process.
2Reliability
If page latch functionality is checked by writing to memory cells, then functionality verification is achieved, but test time increases due to long high voltage cycles
Solution Approach 1:
The patent performs preliminary actions by pre-charging the sense amplifier and preparing the read circuitry before actually reading the page latch data. The page latch is configured to output its contents directly to the sense amplifier through pre-configured word line and bit line connections, allowing the verification read to proceed immediately without the lengthy high voltage programming cycles that would otherwise be required.
Solution Approach 2:
Instead of the conventional approach of writing data to memory cells and then reading back to verify, the patent inverts the sequence by reading the page latch data directly without writing to the memory cells first. This reversal eliminates the time-consuming high voltage write cycles while still achieving verification of page latch functionality by comparing the read data with expected values.
3Reliability
If normal read mode is used to verify memory cell data, then verification is achieved, but additional circuitry and time are required compared to direct page latch reading
Solution Approach 1:
The patent segments the verification process into two independent comparison operations: one comparing shadow memory data with page latch data, and another comparing externally stored data with page latch data. This segmentation allows parallel verification paths and eliminates the need to sequentially perform full memory write cycles followed by reads, significantly improving verification speed while maintaining reliability.
Data Source
AI summary
A method of optimizing memory cell write/read is disclosed. The memory cell write/read is optimized by first reading the memory cell data using the normal mode. Next the page latch data that was used to NV (Non-Volatile) write the memory is also read back directly from the page latches. The two data are then compared to verify a successful and optimized memory cell write/read. NV writes and reads are performed with various high voltage parameters and sense amplifier reference settings to arrive at the most optimal one that gives the largest sense window for best write/read reliability. The page latch read mode is also used as a DFT (Design for Test) test mode to check for page latch functionality and page address uniqueness without having to write the memory cell. The page latch is written with logic data and read out directly using the page latch read mode to verify page functionality.