Semiconductor Memory Refresh Control for Clock Locking Stability
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Solution Overview
Problem
In semiconductor memory apparatuses, the refresh operation often interferes with the locking operation of the clock synchronizing unit, leading to incomplete locking within the predetermined time due to noise generated during the refresh operation, especially when the clock synchronizing unit is reset before completing the locking operation.
Innovation Solution
A refresh control unit is introduced to disable the refresh command signal during the period when the clock synchronizing unit is enabled but the locking operation is not completed, ensuring that the locking operation can be completed stably by preventing the refresh operation from disturbing the synchronization process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the refresh operation is performed during the locking operation period, then the memory can maintain data integrity through refresh, but the noise generated during refresh disturbs the locking operation and prevents timely completion
Solution Approach 1:
The refresh control unit proactively prevents the harmful effect by detecting whether the clock synchronizing unit is in the locking operation period before allowing the refresh operation to proceed. When the locking operation is detected, the refresh control unit blocks the refresh command, thereby preventing power supply noise from disturbing the locking process in advance.
Solution Approach 2:
The refresh control unit acts as an intermediary between the command decoder and the memory cells. It receives refresh commands from the command decoder and controls whether they are passed to the memory cells based on the locking operation status, thereby mediating between the refresh operation and the locking operation to prevent interference.
2Reliability
If the refresh operation is disabled during locking operation, then the locking operation can complete stably without noise interference, but the memory cannot perform refresh operation during this period
Solution Approach 1:
The system dynamically adjusts the availability of refresh operations based on the operational state of the clock synchronizing unit. The refresh control unit continuously monitors the locking operation status and dynamically enables or disables refresh operations accordingly, allowing refresh during non-locking periods while preventing it during locking periods to ensure stability.
Solution Approach 2:
The system operates in periodic cycles where the clock synchronizing unit completes locking operations within a predetermined time window. The refresh control unit utilizes this periodic nature by allowing refresh operations during periods when the locking operation is not active, thereby maintaining productivity while ensuring stability during critical locking periods.
3Adaptability or versatility
If the clock synchronizing unit is reset before locking operation completes, then the system can re-synchronize, but the refresh operation noise prevents complete locking within predetermined time
Solution Approach 1:
After resetting the clock synchronizing unit, the system immediately enters a critical locking period where the refresh control unit proactively blocks all refresh operations to prevent noise interference. This preliminary protective action ensures that the resynchronization process can complete within the predetermined time without being disrupted by refresh-related noise.
Solution Approach 2:
The refresh control unit continuously monitors the locking operation status through feedback signals from the clock synchronizing unit. When the locking operation is detected as incomplete, the feedback mechanism triggers the refresh control unit to block refresh commands, thereby adapting the system behavior to ensure successful resynchronization within the required time window.
Data Source
AI summary
A semiconductor memory apparatus which can restrict a refresh operation for a period when an internal clock is synchronized with an external clock. The semiconductor memory apparatus includes a refresh control unit that disables a refresh command signal which is applied during a period when an enable signal is enabled but a lock-completion signal is not enabled in response to the enable signal outputted from a mode register, the lock-completion signal outputted from a clock synchronizing unit, and the refresh command signal outputted from a command decoder. The clock synchronizing unit can stably complete a locking operation within a predetermined time regardless of power-supply noise and so on.