Multi-Port Memory Deep Power Down Mode Control

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Solution Overview

Problem

Conventional semiconductor memories face challenges in efficiently controlling the activation and deactivation of the deep power down mode, especially in multi-port configurations where multiple processors access internal memory banks via different ports, requiring precise coordination to conserve power in mobile devices.

Innovation Solution

A method for controlling the deep power down mode in multi-port semiconductor memories that involves activating and deactivating the mode in response to control signals received via specific ports, using a combination of clock enable signals, chip selection signals, and write enable signals to manage power consumption effectively.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If the deep power down mode is activated to reduce power consumption in multi-port semiconductor memory, then power consumption is reduced, but the coordination complexity among multiple processors increases

Engineering Contradiction:

Improvepower consumptionVSAvoidcoordination complexity

Core Design Contradiction:

Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent merges the deep power down mode control functions across multiple ports into a unified system. Control signals from any port can trigger DPD mode activation, and the mode state is shared across all ports, simplifying the coordination complexity while maintaining power savings.

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The control mechanism is designed to be universal across all ports of the multi-port semiconductor memory. The same control signals and logic apply regardless of which port initiates the DPD mode, making the system adaptable to multiple processors without increasing complexity.

Inventive Principle:

Principle #6Universality (Multi-functionality)

2Speed

If the deep power down mode is deactivated quickly to respond to processor access requests, then response speed is improved, but power consumption increases

Engineering Contradiction:

Improveresponse speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by moving object

Solution Approach 1:

The patent prepares the system for quick exit from DPD mode by maintaining readiness in the control logic. When a control signal is received to exit DPD mode, the system can immediately transition without lengthy preparation, thus improving response speed while minimizing the time spent in high-power state.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The system dynamically adjusts its state between DPD mode and active mode based on real-time processor access requirements. The control mechanism allows flexible transitions, enabling the system to respond quickly to changing conditions while optimizing power consumption based on actual usage patterns.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS8675440B2Method controlling deep power down mode in multi-port semiconductor memory

Publication Date: 2014.03.18 SAMSUNG ELECTRONICS CO LTD

AI summary

A method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors includes controlling the deep power down mode in the multi-port semiconductor memory such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports.