Semiconductor Memory Device Hammer Refresh Controller
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Solution Overview
Problem
Dynamic random access memory (DRAM) devices face challenges in maintaining data integrity, particularly for dynamic memory cells adjacent to frequently accessed cells, which lose data faster than those adjacent to normally accessed cells, necessitating additional refresh operations beyond standard refresh periods.
Innovation Solution
A semiconductor memory device and system that perform a hammer refresh operation in conjunction with normal refresh operations, utilizing a refresh controller to manage memory cell array blocks, generating specific row addresses, and decoding signals to select word lines for both normal and hammer refresh operations across memory cell array blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If normal refresh operation is performed on all memory cell array blocks, then data retention is maintained for normally accessed cells, but data integrity is compromised for frequently accessed cells (hammer victim cells) that lose data faster
Solution Approach 1:
The patent applies local quality by differentiating refresh operations between normally accessed memory blocks and frequently accessed memory blocks. Specifically, when a hammer refresh operation is detected on a first memory cell array block, the system performs a normal refresh operation on that block while simultaneously performing hammer refresh operations on second and third memory cell array blocks (adjacent blocks). This localized differentiation ensures that frequently accessed cells receive appropriate refresh attention without requiring all blocks to undergo the same refresh protocol, thereby maintaining data integrity while optimizing refresh efficiency.
Solution Approach 2:
The patent implements preliminary action by proactively identifying hammer victim cells through monitoring access patterns and preemptively applying hammer refresh operations before data loss occurs. The system detects when a memory block has been frequently accessed (hammered) and initiates refresh operations on that block and its adjacent blocks before the data in hammer victim cells deteriorates beyond recovery. This preliminary intervention prevents data integrity issues rather than reacting to them after they occur.
2Reliability
If hammer refresh operation is performed on frequently accessed memory cells, then data loss is prevented in those cells, but device complexity increases due to multiple refresh operation types
Solution Approach 1:
The patent applies universality by designing a refresh controller that integrates multiple refresh operation capabilities (normal refresh and hammer refresh) into a single unified control unit. The refresh controller is capable of detecting access patterns, identifying hammer victim cells, and dynamically selecting appropriate refresh operations for different memory cell array blocks. This multi-functional design consolidates what could be separate complex subsystems into one controller, managing data retention for both normally accessed and frequently accessed cells without proportionally increasing overall device complexity.
Solution Approach 2:
The patent implements dynamics by making the refresh operation type adaptive rather than static. The refresh controller continuously monitors memory access patterns and dynamically adjusts which blocks receive normal refresh versus hammer refresh operations. When a block is identified as frequently accessed, the system transitions to applying hammer refresh operations on that block and its adjacent blocks, and can transition back to normal refresh operations when the hammering pattern subsides. This dynamic adaptation allows the system to respond to changing access patterns without requiring complex hardwired logic for every possible scenario.
3Reliability
If multiple memory cell array blocks perform different refresh operations simultaneously, then data integrity is maintained across all blocks, but control complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the memory system into distinct memory cell array blocks that can be independently controlled and refreshed. Each block can be in a different refresh state (normal refresh or hammer refresh) based on its access pattern, allowing parallel execution of different refresh operations without interfering with each other. The refresh controller manages these segmented blocks by identifying which blocks require hammer refresh operations and which can undergo normal refresh, applying the appropriate operation to each segment simultaneously. This segmentation approach simplifies control complexity compared to a monolithic refresh approach by allowing independent, parallel refresh operations on different blocks.
Data Source
AI summary
A semiconductor memory device and a memory system having the same are provided. The semiconductor memory device includes a memory cell array including plural memory cell array blocks, and a refresh controller configured to control the memory cell array blocks to perform a normal refresh operation and a hammer refresh operation. The refresh controller controls one or more third memory cell array blocks excluding a first memory cell array block and one or more second memory cell array blocks adjacent to the first memory cell array block to perform the hammer refresh operation while the normal refresh operation is performed on the first memory cell array block among the memory cell array blocks.