Resistive Memory Read Disturbance Reduction via Distant Column Selection
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Solution Overview
Problem
Resistive memory devices, such as cross-point resistive memory devices, experience read disturbances due to current spikes during read operations, which can damage memory cells and degrade system performance.
Innovation Solution
The implementation of a resistive memory device with a memory cell array, first and second column selection circuits, and a control circuit that determines the distant column selection circuit relative to the selected memory cell, enabling it during read operations to reduce current spikes by varying the voltage level based on the physical distance between the column selection circuit and the memory cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional read operation is performed on a resistive memory cell, then data can be read from the memory cell, but current spikes occur that cause read disturbances and may damage the memory cell
Solution Approach 1:
The patent applies local quality by differentiating the treatment of bit lines based on their distance from the selected memory cell. The control circuit identifies whether a bit line is a first bit line (closer to the selected cell) or a second bit line (farther from the selected cell) and applies different voltage levels accordingly. This localized differentiation reduces current spikes in bit lines that are closer to the selected cell, thereby reducing read disturbances while maintaining reliable data reading.
Solution Approach 2:
The patent employs parameter changes by dynamically adjusting the voltage level applied to bit lines based on their position relative to the selected memory cell. The control circuit varies the voltage parameter - applying a first voltage level to first bit lines and a second voltage level to second bit lines. This parameter variation allows the system to reduce current spikes and minimize read disturbances while maintaining adequate signal strength for accurate data reading.
2Object-affected harmful factors
If the bit line resistance is increased to limit current spikes, then read disturbances are reduced, but the read operation may become unreliable
Solution Approach 1:
The patent applies local quality by differentiating the treatment of bit lines based on their distance from the selected memory cell. The control circuit identifies whether a bit line is a first bit line (closer to the selected cell) or a second bit line (farther from the selected cell) and applies different voltage levels accordingly. This localized differentiation reduces current spikes in bit lines that are closer to the selected cell, thereby reducing read disturbances while maintaining reliable data reading.
Solution Approach 2:
The patent employs parameter changes by dynamically adjusting the voltage level applied to bit lines based on their position relative to the selected memory cell. The control circuit varies the voltage parameter - applying a first voltage level to first bit lines and a second voltage level to second bit lines. This parameter variation allows the system to reduce current spikes and minimize read disturbances while maintaining adequate signal strength for accurate data reading.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively limits current spikes, reducing the risk of read disturbances and maintaining memory system performance by adjusting the bit line resistance through the control circuit's voltage management.
Implementation Method 1
The control circuit is configured during a read operation directed to the selected memory cell to variably set a voltage level of the column selection signal in response to a physical distance between the column selection circuit and the selected memory cell
Implementation Method 2
A cross-point resistive memory device is formed by locating such a memory cell at each of intersections between a plurality of bit lines and a plurality of word lines. In the cross-point resistive memory device, the memory cell is accessed by applying a voltage to both ends of the memory cell, and stores a data value of '1' (low resistance state) or '0' (high resistance state) based on a threshold resistance of the memory cell
Data Source
AI summary
A resistive memory device includes: a memory cell array including resistive memory cells disposed at respective intersections between word lines and bit lines, a first column selection circuit disposed on one side of the memory cell array and configured to selectively connect a bit line connected to a selected memory cell among the resistive memory cells, a second column selection circuit disposed on another side of the memory cell array opposite the first column selection circuit and configured to selectively connect the bit line connected to the selected memory cell, and a control circuit configured to determine a distant column selection circuit from among the first column selection circuit and the second column selection circuit relative to the selected memory cell, and enable the distant column selection circuit during a read operation directed to the selected memory.