NVM Array Testing via Partial Block Current Measurement
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing methods for determining bit states in non-volatile memory (NVM) cells are prone to errors during heating and cooling periods, leading to inaccurate bit error rate calculations, especially at higher temperatures where NVM read windows shrink, necessitating current measurements of all NVM cells which is time-consuming.
Innovation Solution
A method involving heating an NVM array to a target temperature, measuring current distributions of a subset of NVM cells programmed to high and low states, performing pass/fail tests, and calculating bit error rates based on these measurements to compensate for errors, thereby reducing the need for current measurements of all cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If current measurements are performed on all NVM cells at high temperatures, then measurement precision is improved, but loss of time increases significantly
Solution Approach 1:
The NVM array is divided into multiple blocks, and only selected blocks are measured at high temperature. The bit error rate is calculated using data from these measured blocks combined with data from unmeasured blocks, avoiding the need to measure every cell while maintaining statistical accuracy.
Solution Approach 2:
Current distributions obtained from measured blocks are used to represent and infer the characteristics of unmeasured blocks. By analyzing the statistical properties of measured blocks, the system can estimate bit error rates for the entire array without physically measuring every cell.
2Reliability
If temperature is increased to stress test NVM cells, then reliability testing is improved, but measurement precision deteriorates due to shrinking read windows
Solution Approach 1:
Instead of measuring all blocks at high temperature, only a partial subset of blocks is measured. This partial measurement approach provides sufficient statistical data to estimate the bit error rate for the entire array, avoiding the precision loss that would occur if all cells required individual high-temperature measurement.
Solution Approach 2:
The system uses the measured current distributions from selected blocks to calculate and adjust the bit error rate estimate. This feedback mechanism allows accurate reliability assessment even with limited high-temperature measurement data, compensating for the reduced read window precision at elevated temperatures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the accuracy of bit error rate calculations by avoiding errors introduced during temperature changes and shortens test times, enabling reliable bit error rate determination even at high temperatures with degraded NVM read windows.
Implementation Method 1
heating an NVM array to a target temperature
Implementation Method 2
a current signal is generated having a current value based on a resistance of the NVM cell
Data Source
AI summary
A method of testing a non-volatile memory (NVM) array includes heating the NVM array to a target temperature. While the NVM array is heated to the target temperature, a current distribution is obtained by measuring a plurality of currents of a subset of NVM cells of the NVM array, each NVM cell of the NVM array is programmed to one of a logically high state or a logically low state, and first and second pass/fail (P/F) tests on each NVM cell of the NVM array are performed. A bit error rate is calculated based on the current distribution and the first and second P/F tests.