Semiconductor Device Clock Buffer Circuit Power Management
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Solution Overview
Problem
DRAMs consume a significant amount of current due to continuous clocking of internal clock signals, which is undesirable for low-power applications like mobile devices.
Innovation Solution
A semiconductor device that generates an internal clock signal only during required periods by using a clock signal generation circuit, a clock buffer circuit, and a command decoding circuit to synchronize the internal clock with external command signals, allowing for controlled clocking based on specific command types and durations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the internal clock signal is continuously clocked to respond to any command from the memory controller, then the responsiveness and reliability of the DRAM is improved, but the current consumption increases significantly
Solution Approach 1:
The patent applies periodic action by stopping the internal clock signal during idle periods and only activating it when a command is received from the memory controller. The clock signal generation circuit generates the internal clock signal periodically based on command reception, rather than maintaining continuous clocking. This allows the system to maintain responsiveness when needed while significantly reducing current consumption during idle states.
2Use of energy by moving object
If the internal clock signal is stopped to reduce current consumption, then the power efficiency is improved, but the ability to respond to commands is degraded
Solution Approach 1:
The patent implements preliminary action by detecting command signals from the memory controller before the internal clock would naturally stop. The clock signal generation circuit monitors for incoming commands and activates the internal clock signal in advance of the actual clocking operation, ensuring that the system is ready to respond immediately when a command arrives, thus maintaining reliability while enabling power savings during idle periods.
Data Source
AI summary
One semiconductor device includes a clock signal buffer circuit which, in response to activation of a chip selection signal (CS_n), starts generation of an internal clock signal PCLKAR, and internal circuits which operate in synchronization with the internal clock signal PCLKAR. The clock signal buffer circuit suspends generation of the internal clock signal PCLKAR at a second timing if command signals (CA0 to CA9) indicate read commands, and suspends generation of the internal clock signal PCLKAR at a first timing which is earlier than the second timing if the command signals (CA0 to CA9) indicate active commands. According to one embodiment, an internal clock signal is generated only for periods necessary in accordance with external command signals.