Memristor Array Nearest-Neighbor Detection Circuit
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Solution Overview
Problem
The existing systems for detecting the nearest-neighbor vector using memristor arrays face increased circuit scale issues, especially when comparing multiple vectors, and require analog-to-digital conversion, which further enlarges the circuit complexity.
Innovation Solution
A computer system is designed with a memristor array that includes an adder circuit to calculate sum voltages by combining difference voltages generated from current flows in bit lines, and a detection circuit to identify the bit line with the maximum sum voltage, thereby reducing the circuit scale by using a single memristor array for nearest-neighbor vector detection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple vectors are compared using existing memristor array systems, then nearest-neighbor detection capability is improved, but circuit scale increases
Solution Approach 1:
The patent merges multiple vector comparison operations into a single memristor array by encoding multiple vectors in different memory blocks within the same array structure. The adder circuit combines results from multiple blocks, enabling multi-vector comparison without requiring separate arrays for each vector, thus improving adaptability while controlling circuit scale.
Solution Approach 2:
The memristor array is designed to perform multiple functions: storing multiple vectors, performing parallel comparisons, and detecting nearest neighbors all within a single unified structure. The same array handles different vector inputs and comparison operations, making the system universal rather than requiring dedicated circuits for each specific comparison task.
2Measurement precision
If analog-to-digital conversion is implemented for precise vector comparison, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent replaces the conventional approach of analog-to-digital conversion with a direct analog computation method using the adder circuit. Instead of converting analog currents to digital values for comparison, the system performs analog addition of currents directly in the circuit, maintaining precision while avoiding the complexity of ADC components and digital processing stages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for efficient detection of the nearest-neighbor vector with reduced circuit complexity, enabling the system to handle multiple vector comparisons without the need for extensive analog-to-digital conversion, thus minimizing the overall circuit scale.
Implementation Method 1
A cross-point type memristor array in which a memristor a resistance value of which changes according to a current is arranged at an intersection between a word line and a bit line
Implementation Method 2
an adder circuit configured to obtain sum voltages for the plurality of second bit lines by adding a plurality of first voltages to difference voltages
Implementation Method 3
a detection circuit configured to detect a second bit line that corresponds to a maximum value of the sum voltages
Data Source
AI summary
A computer includes: a memristor array including memristors arranged at intersections between word lines and a first bit line in the memristor array and at intersections between the word lines and second bit lines in the memristor array; an adder circuit configured to obtain sum voltages for the second bit lines by adding first voltages generated according to currents that flow in the second bit lines when a first pattern is supplied to the word lines to difference voltages between a reference voltage generated according to a current that flows in the first bit line when a second pattern is supplied to the word lines and second voltages generated according to currents that flow in the second bit lines when a second pattern is supplied to the word lines; and a detection circuit that detects a second bit line that corresponds to a maximum value of the sum voltages.