Split Global Bitline Circuit for Multi-Bank SRAM Power Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Multi-bank SRAMs face high power consumption during access operations due to the shared global bitline, which results in increased capacitance and RC delay, affecting performance and leading to potential false reads.
Innovation Solution
The design splits the global bitline into a far global bitline and a near global bitline, each connected to logic gates, eliminating the need for NMOS transistors as multiplexers and pre-charge drivers, thereby reducing power consumption and RC delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a shared global bitline is used to connect multiple memory banks, then device complexity is reduced, but power consumption increases due to increased capacitance and RC delay
Solution Approach 1:
The global bitline is segmented into multiple separate global bitlines, each serving a specific subset of memory banks. This segmentation reduces the capacitance and RC delay of each individual global bitline compared to a single shared global bitline, thereby reducing power consumption during access operations while maintaining manageable device complexity through organized bank-group assignments
2Ease of operation
If a shared global bitline is used among multiple banks, then ease of operation is improved, but reliability deteriorates due to floating states causing false reads
Solution Approach 1:
By dividing the global bitline into separate segments assigned to specific bank groups, the patent eliminates the floating state problem that occurs in shared global bitlines. Each segmented global bitline has a defined connection state during its assigned bank group's access operation, preventing false reads and improving reliability while maintaining ease of operation through dedicated pathways
Solution Approach 2:
Different global bitlines are assigned to different bank groups based on their spatial or functional characteristics. This local quality assignment ensures that each global bitline operates in an optimal state for its specific bank group, with defined connection and disconnection patterns that prevent floating states and ensure reliable read operations
3Manufacturing precision
If multiple memory banks share a common global bitline, then manufacturing precision requirements are reduced, but loss of energy increases due to capacitance charging/discharging
Solution Approach 1:
The global bitline is divided into multiple smaller segments, each connecting to a specific bank group. This segmentation reduces the total capacitance that needs to be charged and discharged during each access operation compared to a single large shared global bitline, thereby reducing energy loss while maintaining relaxed manufacturing precision requirements through standardized connection patterns
Data Source
AI summary
A multi-bank memory includes: a pair of far banks coupled to a first word line and a first pair of local bitlines, respectively; a pair of near banks coupled to a second word line and a second pair of local bitlines, respectively; a far global bit line coupled to the first pair of local bitlines; a first NAND gate having a first input coupled to the second pair of local bitlines and a second input coupled to the far global bit line; a near global bit line coupled to the output of the first NAND gate; and a global input/output (I/O) circuit, coupled to the near global bit line, for outputting data.