Self-Refresh Power Control via Bank Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The miniaturization of semiconductor devices leads to increased leakage currents during power-down modes, which degrades the overall performance of memory devices, especially during self-refresh operations where power is only supplied to circuits performing refresh operations.
Innovation Solution
A memory device that includes a refresh control circuit generating self-refresh commands and addresses, a group management circuit classifying these addresses into groups, and a supply control circuit activating power only to specific groups of word lines, minimizing current consumption by selectively enabling power to selected groups during self-refresh operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If power is supplied to all circuits during self-refresh operation, then refresh operation reliability is improved, but power consumption increases
Solution Approach 1:
The memory device is divided into multiple banks, with each bank independently performable refresh operations. During self-refresh, only selected banks are activated while others remain in power-down mode, segmenting the power consumption across different operational regions of the memory device
Solution Approach 2:
Different power supply strategies are applied to different regions (banks) of the memory device based on local needs. Banks requiring refresh operations receive full power supply, while banks that can tolerate power-down mode receive reduced or no power, creating localized quality differences in power delivery
2Use of energy by moving object
If power is cut off to reduce leakage current, then power consumption is reduced, but data retention capability deteriorates
Solution Approach 1:
The power supply state of each bank is dynamically adjusted based on operational requirements. Banks can transition between active state (full power) and power-down state (reduced power) depending on whether they need to perform refresh operations or can rely on previous refresh states
Solution Approach 2:
Refresh operations are performed periodically in selected banks to maintain data retention. By cycling through different bank combinations for refresh operations, the system ensures data integrity while allowing other banks to enter power-saving modes
3Reliability
If all word line control circuits are enabled during self-refresh, then refresh coverage is improved, but current consumption increases
Solution Approach 1:
Word line control circuits are segmented and grouped according to their associated banks. During self-refresh, only the control circuits corresponding to active banks are enabled, while control circuits for banks in power-down mode remain disabled, segmenting the current consumption pathway
Solution Approach 2:
The patent extracts and disables unnecessary control circuits from the active set during self-refresh operation. By identifying and removing the need for certain word line control circuits based on which banks are active, the system eliminates redundant current consumption while maintaining necessary refresh coverage
Data Source
AI summary
A memory device includes: a refresh control circuit configured to generate a self-refresh command and a refresh address, word line control circuits configured to control a refresh operation of a plurality of word lines, a group management circuit configured to classify N address groups by grouping the refresh addresses to be generated by the refresh control circuit and to select from the N address groups, a current address group including a refresh address to be currently generated and a subsequent address group including a refresh address to be generated after the current address group according to the predetermined order, a row control circuit configured to group the plurality of word line control circuits with N control signals respectively corresponding to the N address groups, respectively, and a supply control circuit configured to activate signals corresponding to the current and subsequent address groups among the N control signals.