Floating Body Transistor Memory Cells Using Complementary Bit Lines
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Solution Overview
Problem
Conventional floating body transistor capacitorless memory cells are prone to reading errors due to overlapping drain current distributions and require reference cells and complex current sense amplifiers, which hinder device integration and increase processing time.
Innovation Solution
The implementation of complementary bit lines and voltage sense amplifiers to restore and write threshold voltages of floating body transistor capacitorless memory cells, eliminating the need for reference cells and simplifying the circuitry by using parasitic capacitance for capacitive coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional floating body transistor capacitorless memory cells are used, then device integration is increased, but reading errors occur due to overlapping drain current distributions
Solution Approach 1:
The patent introduces complementary bit lines as an intermediary element between the memory cells and the sense amplifier. These complementary bit lines carry complementary signals that enable differential sensing, effectively mediating the read operation to distinguish overlapping current distributions through voltage differential amplification rather than direct current comparison.
Solution Approach 2:
The patent replaces the conventional current sense amplifier mechanism with a voltage sense amplifier. Instead of directly sensing and comparing drain currents (mechanical/electrical current measurement), the system converts the signal to voltage differential on complementary bit lines and amplifies that voltage difference, substituting one sensing mechanism for another more effective one.
2Reliability
If reference cells and current sense amplifiers are used, then reading accuracy is improved, but device complexity and processing time increase
Solution Approach 1:
The patent extracts and eliminates the reference cell component from the memory system. By using complementary bit lines that inherently provide differential signaling, the system no longer requires separate reference cells to establish a baseline for comparison, simplifying the overall device structure while maintaining reading accuracy.
Solution Approach 2:
The patent merges the functions of reference cells and current sense amplifiers into a single voltage sense amplifier system. The complementary bit lines and voltage sense amplifier combine multiple functions into one integrated circuit block, reducing the total number of components and interconnections required.
3Reliability
If reference cells are used, then reading accuracy is improved, but processing time increases due to additional refresh operations
Solution Approach 1:
The patent removes reference cells from the system architecture, thereby eliminating the need for their periodic refresh operations. This extraction of the reference cell subsystem directly eliminates the associated time loss from refresh cycles while maintaining reading accuracy through the complementary bit line differential sensing mechanism.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces reading errors, enhances memory device density, and eliminates the need for reference cells and complex current sense amplifiers, improving operational efficiency and reducing processing time.
Implementation Method 1
a voltage sense amplifier coupled between the complementary first and second bit lines which amplifies a voltage differential between the complementary first and second bit lines
Implementation Method 2
The implementation of complementary bit lines and voltage sense amplifiers to restore and write threshold voltages of floating body transistor capacitorless memory cells, eliminating the need for reference cells and simplifying the circuitry by using parasitic capacitance for capacitive coupling
Data Source
AI summary
In one aspect, a semiconductor memory device is provided which includes complementary first and second bit lines, a unit memory cell including complementary first and second floating body transistor capacitorless memory cells respectively coupled to the complementary first and second bit lines, and a voltage sense amplifier coupled between the complementary first and second bit lines which amplifies a voltage differential between the complementary first and second bit lines.