Semiconductor Data Input Buffer Impedance Control

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Solution Overview

Problem

Existing semiconductor apparatuses face challenges in accurately controlling impedance for data output, which affects the characteristics of data transmission and reception, necessitating a more efficient method for impedance management.

Innovation Solution

A semiconductor apparatus with a data input buffer that generates write data and output level detection signals, coupled with an impedance adjustment circuit that adjusts and readjusts impedance signals based on external resistor values and output level detection signals, ensuring optimal impedance matching during write and read operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional fixed impedance control methods are used in data buffers, then the circuit structure remains simple, but the data output characteristics cannot be accurately controlled and impedance matching with external resistors is poor

Engineering Contradiction:
Improveimpedance control accuracyVSAvoidbuffer circuit complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies dynamics by making the impedance adjustment signals可调 (adjustable) rather than fixed. The first and second impedance adjustment signals are dynamically modified based on output level detection signals from the buffer, enabling the output impedance to adapt to different operating conditions and achieve accurate impedance matching with external resistors.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent implements feedback by using output level detection signals to monitor the buffer output and automatically adjusting the impedance adjustment signals accordingly. This closed-loop feedback mechanism enables precise control of data output characteristics by continuously optimizing the impedance matching between the buffer and external resistors.

Inventive Principle:
Principle #23Feedback

2Reliability

If dynamic impedance adjustment is implemented to improve data transmission accuracy, then impedance matching improves, but the circuit structure and control complexity increase

Engineering Contradiction:
Improvedata transmission accuracyVSAvoidimpedance control circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies self-service by enabling the buffer to automatically adjust its own impedance characteristics. The buffer monitors its own output level and autonomously modifies its impedance adjustment signals without requiring external intervention, thereby improving data transmission accuracy while minimizing the need for additional complex external control circuits.

Inventive Principle:
Principle #25Self-service

3Reliability

If multiple impedance adjustment signals are used to control different output characteristics, then data transmission reliability improves, but the control signal management becomes more complex

Engineering Contradiction:
Improvedata output characteristic controlVSAvoidcontrol signal management
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The patent merges the functions of multiple impedance adjustment signals by integrating their control into a unified feedback mechanism. The first and second impedance adjustment signals are coordinated through common output level detection signals, allowing simultaneous control of different output characteristics while simplifying the overall control signal management through centralized feedback-based adjustment.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11562777B2Data input buffer and semiconductor apparatus including the same
Publication Date: 2023.01.24 SK HYNIX INC
  • US11562777B2 patent drawing
  • US11562777B2 patent drawing
  • US11562777B2 patent drawing

AI summary

A semiconductor apparatus includes a data input buffer configured to generate write data by receiving data that is input through a data input/output unit during a write operation section and configured to generate an output level detection signal by detecting a voltage level of the data I/O unit during a read operation section.