SRAM Word Line Driver Circuits with Reduced Bit Line Pre-charge Voltage
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Solution Overview
Problem
Current SRAM memory devices face challenges in reducing power consumption, achieving faster signal provision, reliable sensing, and minimizing soft error rates, particularly due to high energy sub-atomic particle exposure.
Innovation Solution
The implementation of six-transistor (6T) SRAM bit cells with bit lines pre-charged to ½ VDD and low VT pass transistors, which reduces power consumption, enhances write and pre-charge speeds, and increases immunity to soft errors by employing cross-coupled p- and n-transistors for dynamic sensing, while maintaining comparable area and stability to conventional 6T bit cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit lines are pre-charged to full VDD, then sufficient voltage margin is available for reliable sensing, but power consumption increases and write speed decreases
Solution Approach 1:
The patent changes the pre-charge voltage parameter from full VDD to ½ VDD, fundamentally altering the voltage operating point of the bit lines. This parameter change enables lower power consumption while maintaining reliable sensing through the combined effect of reduced capacitive charging energy and the differential sensing mechanism that amplifies small voltage differences from the bit cell
2Reliability
If bit lines are pre-charged to full VDD, then sufficient voltage swing is available for reliable signal detection, but write speed and pre-charge speed decrease
Solution Approach 1:
By changing the pre-charge voltage parameter to ½ VDD, the patent reduces the voltage swing required during write and pre-charge operations. This parameter change directly improves speed by reducing the time constant for capacitive charging/discharging, while the differential sensing mechanism compensates for the reduced absolute voltage swing to maintain detection reliability
3Area of stationary object
If conventional 6T bit cell structure is used, then area efficiency is maintained, but soft error rate increases due to lower immunity to high energy particles
Solution Approach 1:
The patent segments the sensing function into two independent paths through the use of separate n-type and p-type bit lines, each with its own sensing amplifier. This segmentation creates redundancy in the sensing mechanism, where the differential comparison between two independent paths provides inherent immunity to soft errors caused by high energy particles, while maintaining the compact 6T bit cell area
Data Source
AI summary
A memory device comprising a plurality of static random access memory (SRAM) bit cells, and a word line driver coupled to provide a word line signal to the bit cells. The word line driver receives a global word line signal that remains active while the word line signal is asserted and subsequently de-asserted, and the word line signal is coupled between a positive supply voltage (VDD) and a supply voltage below ground (VN).