Semiconductor Memory Data I/O Unit Without Repeaters

Solution Overview

Problem

Conventional semiconductor memory devices face inefficiencies in data transfer between global lines, particularly in training modes, due to the reliance on repeaters that increase device size and complexity.

Innovation Solution

A semiconductor memory device design that eliminates the need for repeaters by using a multi-purpose register to load and transfer data between global lines, allowing efficient data transfer without repeaters, especially in extended bandwidth modes like X16, by utilizing data I/O units that operate independently of bandwidth options.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If repeaters are used to transfer data between global lines in training mode, then data transfer capability is improved, but device size and complexity increase

Engineering Contradiction:

Improvedata transfer capabilityVSAvoiddevice size

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The data I/O unit is designed to perform multiple functions: it can transfer data between global lines in training mode without repeaters, and it can also transfer data between data pads and global lines in normal modes. This multi-functional design eliminates the need for separate repeater circuits while maintaining data transfer capability across different operational modes.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent combines the functions of repeaters and data I/O units into a single integrated data I/O unit. This merging of functions allows the device to achieve both data transfer between global lines (traditionally requiring repeaters) and data pad interfacing (traditionally requiring I/O units) through a unified circuit structure, thereby reducing overall device complexity.

Inventive Principle:

Principle #5Merging (Combining)

2Adaptability or versatility

If repeaters are used to enable training mode operation, then training data transfer is improved, but the number of circuit components increases

Engineering Contradiction:

Improvetraining mode operationVSAvoidnumber of circuit components

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The data I/O unit is designed to perform multiple functions: it can transfer data between global lines in training mode without repeaters, and it can also transfer data between data pads and global lines in normal modes. This multi-functional design eliminates the need for separate repeater circuits while maintaining data transfer capability across different operational modes.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The data I/O unit dynamically adapts its operation based on the operational mode. In training mode, it configures itself to transfer data between global lines directly. In normal modes, it configures itself to transfer data between data pads and global lines. This dynamic reconfiguration allows a single circuit to replace multiple static circuits (repeaters and I/O units), reducing component count.

Inventive Principle:

Principle #15Dynamics

3Adaptability or versatility

If separate data I/O units are used for different bandwidth modes, then bandwidth adaptability is improved, but device complexity increases

Engineering Contradiction:

Improvebandwidth mode supportVSAvoiddevice structure

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The first data I/O unit is designed as a universal interface that can operate across all bandwidth modes (X8, X16, etc.). It selectively transfers data between the first data pad and various global lines (first, second, third, and fourth global lines) depending on the active bandwidth mode, eliminating the need for separate dedicated I/O units for each mode.

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The data I/O unit dynamically adapts its operation based on the operational mode. In training mode, it configures itself to transfer data between global lines directly. In normal modes, it configures itself to transfer data between data pads and global lines. This dynamic reconfiguration allows a single circuit to replace multiple static circuits (repeaters and I/O units), reducing component count.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentUS9530465B2Semiconductor memory device

Publication Date: 2016.12.27 SK HYNIX INC

AI summary

A semiconductor memory device includes a first global line suitable for inputting/outputting data from/to a first bank, a second global line suitable for inputting/outputting data from/to a second bank, a multi-purpose register (MPR) suitable for loading data having a predetermined value on the first global line in a training mode, a first data input/output (I/O) unit suitable for inputting/outputting data between one of the first and second global lines and a first data pad and selectively transferring data loaded on the first global line to the second global line in response to a bandwidth option in the training mode, and a second data I/O unit enabled in response to the bandwidth option, suitable for inputting/outputting data between the second global line and a second data pad.