Scannable-latch RAM Fills SRAM Register File Gap
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Solution Overview
Problem
There is a gap in memory solutions between register files and SRAMs in terms of size and power requirements, as register files have a smaller operational overhead but larger size per bit, while SRAMs are more suitable for intermediate memory needs.
Innovation Solution
A scannable-latch random access memory (SLRAM) design that includes a write port, read port, and rows of memory cells with functional and scan data inputs/outputs, allowing for both functional and scan modes of operation, enabling efficient memory operations and built-in testing capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If register files are used for memory storage, then operational overhead is reduced, but size per bit increases significantly
Solution Approach 1:
The memory array is segmented into multiple banks (first bank, second bank, third bank, fourth bank) that can be independently accessed and tested. Each bank contains multiple rows of memory cells that can be selectively activated through row select signals (R0S, R1S, R2S, R3S), allowing the large memory structure to be divided into manageable units for both operation and testing purposes.
Solution Approach 2:
The memory structure supports multiple operational modes including normal read/write operations and scan testing mode. The same memory cells can function as storage elements during normal operation and as testable scan chains during manufacturing testing, eliminating the need for separate test structures and reducing overall device complexity.
2Area of stationary object
If SRAMs are used for memory storage, then size per bit is reduced, but operational overhead and hardware requirements increase
Solution Approach 1:
The patent extracts and eliminates the need for complex SRAM-specific hardware components such as refresh circuits and sense amplifier circuits by using a latch-based memory cell design. The latch structure inherently maintains data without requiring external refresh mechanisms, and the memory cell output is directly accessible without needing sense amplification, thereby reducing operational overhead while maintaining compact size.
Solution Approach 2:
The memory cell design uses latch elements with complementary clock signals (CK and CK bar) to control data storage and retrieval. By changing the operational parameters from traditional SRAM six-transistor cells to latch-based cells with clocked control, the patent achieves reduced size per bit while simplifying the operational requirements and reducing hardware overhead.
3Reliability
If scan testing capability is added to memory, then manufacturing testing effectiveness improves, but device complexity increases
Solution Approach 1:
The scan testing capability is merged with the normal memory operation structure. The same memory cells that store data during normal operation form the scan chains during testing. The scan data input connects to first memory cells in each bank, and scan data output connects to last memory cells, allowing test data to flow through the memory cells in a shifted register fashion while using the existing memory cell infrastructure, thereby improving testing effectiveness without proportionally increasing device complexity.
Solution Approach 2:
The memory structure dynamically switches between normal operational mode and scan testing mode through the scan enable signal. When scan enable is activated, the memory cells operate as a scan chain for testing; when deactivated, they return to normal read/write operations. This dynamic reconfiguration allows a single structure to serve multiple purposes, improving testing capability while minimizing permanent complexity additions.
Data Source
AI summary
A scannable-latch random access memory (SLRAM) is disclosed. The SLRAM includes two rows of memory cells. The SLRAM includes a functional data input, a scan data input, a first and second functional data outputs, a scan data output, and a scan enable. The functional data input is connected to a first memory cell in a first and second rows of memory cells. The scan data input is connected to the first memory cell in the first or second row of memory cells. The first and second functional data outputs are connected to a last memory cell in the first and second row of memory cells, respectively. The scan data output is connected to the last memory cell in the first or second row of memory cells. The scan enable allows data to be output from the scan data output or the first and second functional data outputs.