Ferroelectric Memory Test Method for Plate Line Signal Delay
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Solution Overview
Problem
Ferroelectric memory stress tests are prolonged due to delays in signal rise and fall times across plate lines, affecting the efficiency of testing multiple memory cells simultaneously.
Innovation Solution
A test method for ferroelectric memory that applies stress voltage between the bit line and plate line, with specific control of block select, reset, and word lines to ensure all cell transistors are ON, allowing simultaneous stress testing of multiple memory cells by controlling the potential of these lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If stress voltage is applied to multiple memory cells simultaneously through shared plate lines, then testing efficiency is improved, but signal rise and fall delays increase causing prolonged test time
Solution Approach 1:
The patent divides the memory cell array into multiple independent cell blocks, each with its own dedicated plate line. This segmentation allows simultaneous stress testing of multiple cell blocks without signal interference, resolving the contradiction between testing efficiency and test time by enabling parallel testing while avoiding plate line delays
Solution Approach 2:
The patent introduces a plate line selection circuit that acts as an intermediary to selectively connect different plate lines to different cell blocks. This mediator enables flexible configuration where multiple plate lines can operate simultaneously without mutual interference, thus improving testing efficiency while maintaining fast signal transitions
2Productivity
If multiple plate lines are driven simultaneously for stress testing, then more memory cells can be tested in parallel, but signal delays across plate lines increase
Solution Approach 1:
The memory array is segmented into multiple cell blocks with dedicated plate lines, allowing parallel driving of multiple plate lines without signal delays affecting all lines simultaneously. Each plate line operates independently, maintaining fast signal transitions while enabling parallel testing of multiple cell blocks
Solution Approach 2:
The patent extends the testing architecture from a single plate line to multiple plate lines operating in parallel across different cell blocks. This dimensional expansion allows simultaneous stress testing of multiple memory regions without the signal delays that would affect a single shared plate line
Data Source
AI summary
A ferroelectric memory includes a cell block that includes: a block select transistor arranged between a bit line and a local bit line; memory cells arranged between the local bit line and a plate line, each of the memory cells contains a cell transistor and a ferroelectric capacitor connected in series; and a reset transistor arranged between the local bit line and the plate line. A test method for the ferroelectric memory includes: applying a potential that allows the cell transistors to be ON to the word lines; applying a potential that allows the reset transistor to be OFF to the reset line; applying a potential that allows the block select transistor to be ON to the block select line; and applying a stress voltage between the bit line and the plate line.