SRAM Read Write Assist Using Reduced Voltage Generation
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Solution Overview
Problem
Existing SRAM technologies require complex generation of multiple power supply voltages to assist read and write operations, increasing complexity and inefficiency.
Innovation Solution
An SRAM design using a pair of P channel transistors with a normal power supply voltage and a generated reduced voltage for read and write assist, where sources are connected to the reduced voltage and bodies are connected to the normal supply voltage during operations, effectively assisting both read and write with only one additional voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If two bitcell power supplies (one above VDD and one below VDD) are provided to assist read and write operations, then the reliability of read and write operations is improved, but the device complexity increases due to the need for generating two power supply voltages different from VDD
Solution Approach 1:
The patent changes the voltage parameter by using only one reduced voltage (below VDD) instead of requiring two different voltages (one above and one below VDD). The read assist is achieved by applying the reduced voltage to the source of P-channel transistors during read operations, while write assist is achieved by applying the reduced voltage to the body terminal of P-channel transistors during write operations. This parameter change simplifies the voltage generation requirement from two voltages to one reduced voltage.
2Reliability
If one power supply voltage exceeds VDD to assist read operations, then the read assist effectiveness is improved, but the device complexity increases due to the need for generating a voltage higher than VDD
Solution Approach 1:
The patent eliminates the need for a voltage above VDD by using the reduced voltage (below VDD) in combination with the normal VDD supply. During read operations, the reduced voltage is applied to the source of P-channel transistors while the body remains at VDD, creating the necessary voltage differential for effective read assist without requiring any voltage to exceed VDD.
3Reliability
If separate voltage generation circuits are implemented for read and write assist, then the assist effectiveness is improved, but the device complexity and area increase
Solution Approach 1:
The reduced voltage generation circuit serves multiple functions: it provides voltage for read assist when applied to the source of P-channel transistors, and it provides voltage for write assist when applied to the body terminal of P-channel transistors. This multi-functional approach eliminates the need for separate voltage generation circuits for read and write operations, reducing overall circuit complexity and area.
Data Source
AI summary
A memory includes an SRAM bitcell including a pair of cross-coupled inverters, wherein a first inverter of the pair includes a first device having a body and a second inverter of the pair includes a second device having a body. A first selection circuit has a first input coupled to a first supply voltage terminal, a second input coupled to a second supply voltage terminal, and an output coupled to a first current electrode of the first device and to a first current electrode of the second device. A second selection circuit has a first input coupled to the first supply voltage terminal, a second input coupled to the second supply voltage terminal, and an output coupled to the body of each of the first and second devices. A word line coupled to the SRAM bitcell is driven by a word line driver coupled to the first supply voltage terminal.