SRAM Write Assist Circuit with Negative Boost and Clamping
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Solution Overview
Problem
Existing write assist techniques for SRAM devices, such as negative boosting, face issues like unintended activation of unselected bit switches, power wastage, and timing inaccuracies, which affect the performance and efficiency of write operations in memory arrays.
Innovation Solution
The proposed solution involves a write assist apparatus with a common discharge node, negative boost circuitry, and a clamping device to limit the negative voltage, along with an interlock circuit using a mimic bit line to control the timing of the discharge and boost sequence, ensuring precise voltage application and preventing unselected bit switch activation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If negative boosting is used to discharge bit line to voltage below ground, then write margin is improved, but unselected bit switches may be inadvertently activated
Solution Approach 1:
The patent applies different voltage levels to different regions of the memory array by using locally-controlled write drivers. Selected bit lines receive the full negative boost voltage for improved write margin, while unselected bit lines are maintained at ground potential through local discharge transistors, preventing unwanted activation of unselected bit switches.
Solution Approach 2:
The memory array is segmented into selected and unselected regions through the use of word line-controlled discharge transistors. This segmentation allows independent voltage control of bit lines in different regions, enabling negative boosting only where needed while protecting unselected regions from harmful voltage effects.
2Reliability
If negative boosting is applied too soon before complete discharge, then bit line does not reach optimum voltage, but if applied too late, then cycle time increases
Solution Approach 1:
The write driver begins discharging the bit line to ground potential in advance through the discharge transistor before the negative boost is applied. This preliminary discharge action ensures the bit line is ready to receive the negative boost voltage at the optimal moment, achieving the target voltage level without delaying the write operation and incurring cycle time penalties.
Solution Approach 2:
The discharge transistor remains active continuously during the write operation, maintaining the bit line at ground potential throughout. This continuous discharge action ensures smooth transition to negative boosting without interruption or timing delays, optimizing both voltage achievement and cycle time.
3Productivity
If access transistors are optimized for write operation with reduced on-resistance, then write performance improves, but cell stability during read operation deteriorates
Solution Approach 1:
The access transistor on-resistance is made dynamic rather than fixed. During write operations, the transistors operate with lower effective resistance to improve write performance. During read operations, the transistors naturally present higher resistance, maintaining cell stability. The negative boosting technique further assists write operations without requiring permanently low resistance, allowing the system to adapt resistance characteristics to operational needs.
Data Source
AI summary
An apparatus for implementing a write assist for a memory array includes a common discharge node configured to provide a discharge path for precharged write data lines and bit lines selected during a write operation of the memory array; negative boost circuitry configured to introduce a voltage lower than a nominal logic low supply voltage onto the common discharge node following the discharge of the common discharge node, write data lines and bit lines; and a clamping device coupled to the common discharge node, the clamping device configured to limit the magnitude of negative voltage applied to common discharge node by the negative boost circuitry so as to prevent activation of non-selected bit switches.