Multi-die DRAM Bank Interconnect via Dynamic Buffer Switching
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Solution Overview
Problem
The complexity of electronic circuits in multi-die stacks, particularly due to increased contact density, leads to reduced efficiency and speed as existing configurations require extensive circuitry and numerous contacts to interconnect memory banks, making it challenging to achieve high performance.
Innovation Solution
The implementation of buffers that dynamically select contacts to connect with a currently selected memory bank, reducing the number of contacts and circuitry needed, thereby improving the performance characteristics of the multi-die stack by optimizing signal line connections through a field of contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple memory banks are interconnected using extensive circuitry and numerous contacts in existing multi-die stack configurations, then the connectivity between memory banks is achieved, but the device complexity and number of contacts increase significantly
Solution Approach 1:
The patent implements a universal interconnect structure where a single set of buffer lines and cross-bar switches can dynamically connect any memory bank to any contact, allowing the same physical infrastructure to serve multiple memory banks through time-multiplexed connections rather than requiring dedicated circuitry for each bank
Solution Approach 2:
The patent employs dynamic switching mechanisms where buffer lines and cross-bar switches can be reconfigured in real-time to establish different connection paths between memory banks and contacts, enabling flexible routing that adapts to the currently active memory bank rather than using fixed static connections
2Adaptability or versatility
If the number of contacts on the die is increased to support more memory banks, then the memory bank connectivity is improved, but the manufacturing precision and ease of manufacture deteriorate due to reduced minimum feature size and enhanced complexity
Solution Approach 1:
The patent transitions from a two-dimensional planar arrangement of contacts to a three-dimensional vertical stack configuration where multiple dies are stacked and interconnected through through-silicon vias (TSVs), effectively adding a vertical dimension to the interconnect architecture to reduce lateral contact density requirements
Solution Approach 2:
The patent introduces buffer lines as intermediary elements between memory banks and contacts, which act as intermediate connection points that reduce the direct connectivity requirements between memory banks and external contacts, thereby reducing the number of high-precision contacts needed on the die surface
3Adaptability or versatility
If extensive circuitry is used to connect memory banks to contacts, then the connectivity coverage is improved, but the speed and efficiency of the multi-die stack are reduced
Solution Approach 1:
The patent pre-establishes buffer lines that are permanently connected to contacts, and only dynamically activates the specific cross-bar switches and buffer segments needed for the currently active memory bank, avoiding the need to reconfigure entire signal paths and reducing signal transmission delay
Solution Approach 2:
The patent divides the interconnect structure into segmented regions including buffer line segments, cross-bar switch segments, and memory bank segments, allowing independent optimization and control of each segment to minimize overall signal path length and improve transmission speed
Data Source
AI summary
The various embodiments described herein include memory dies and methods for memory die communications. In one aspect, a method is performed at a first memory die with a plurality of memory banks and a plurality of contacts. The method includes: (1) coupling a first memory bank of the plurality of memory banks to a second memory die via the plurality of contacts; (2) transmitting data between the first memory bank and the second memory die via the plurality of contacts; and (3) receiving a control signal to couple a second memory bank of the plurality of memory banks to the second memory die. The method further includes, in response to receiving the control signal, coupling the second memory bank to the second memory die via the plurality of contacts; and transmitting data between the second memory bank and the second memory die via the plurality of contacts.