Non-volatile SRAM Segmentation for Leakage Reduction
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Solution Overview
Problem
The increasing power consumption due to leakage current in sleep mode of System on Chip (SoC) devices, particularly in static random access memory (SRAM), which affects device stability and lifespan, as existing non-volatile memories cannot match the operation speed of SRAM.
Innovation Solution
Integration of a non-volatile static random access memory (NV-SRAM) that combines SRAM and non-volatile memory (NVM) components, utilizing a latch unit, switches, and NVMs to enable power cutoff during sleep mode while maintaining high-speed access characteristics, by modulating voltage states to record and recall data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If SRAM is used in sleep mode to maintain data, then data retention is achieved, but power consumption increases due to leakage current
Solution Approach 1:
The memory system is segmented into two distinct parts: SRAM for high-speed data access during active mode, and NVM for data retention during sleep mode. This segmentation allows each component to operate in its optimal mode, with the SRAM being powered down during sleep to eliminate leakage current while NVM maintains data without power
Solution Approach 2:
Control logic acts as an intermediary between the SRAM and NVM components, managing data transfer and coordination. During mode transitions, the control logic ensures data is properly transferred from SRAM to NVM before powering down SRAM, and vice versa during wake-up, preventing data loss while enabling power savings
2Use of energy by moving object
If NVM is used to reduce power consumption in sleep mode, then power consumption decreases, but operation speed decreases compared to SRAM
Solution Approach 1:
The system dynamically switches between SRAM and NVM based on operational mode. During active mode, SRAM provides high-speed access for frequent operations. During sleep mode, NVM maintains data with zero power consumption. This dynamic adaptation allows the system to optimize for speed when needed and for power savings when idle
Solution Approach 2:
The memory subsystem is designed with multi-functionality, where the same memory system can operate in two distinct modes: high-speed SRAM mode during active operation and low-power NVM mode during sleep. This universality allows a single system to serve both high-performance and low-power requirements without needing separate dedicated memory systems
3Area of stationary object
If process shrink is implemented to reduce IC surface area, then fabrication cost is reduced and performance is improved, but leakage current increases leading to higher power consumption
Solution Approach 1:
The system changes operational parameters based on mode: during active mode, SRAM operates with standard leakage characteristics benefiting from process shrink. During sleep mode, the system transitions to NVM which has fundamentally different electrical characteristics with negligible leakage current, effectively neutralizing the leakage increase from process shrink
Data Source
AI summary
A non-volatile static random access memory (NV-SRAM) including a latch unit, a first switch, a second switch, a first non-volatile memory (NVM), and a second NVM and an operation method thereof are provided. First terminals of the first and the second switch are respectively connected to a first and a second terminal of the latch unit. Second terminals of the first and the second switch are respectively connected to a first and a second bit line. Control terminals of the first and the second switch are connected to a word line. First terminals of the first and the second NVM are respectively connected to the first and the second terminal of the latch unit. Second terminals of the first and the second NVM are respectively connected to the first and the second bit line. Enable terminals of the first and the second NVM are connected to an enable line.