FinFET Memory Cell Shared Semiconductor Fins
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Solution Overview
Problem
Dynamic Random-Access Memories (DRAMs) are inefficient in access speed and power consumption, leading to the 'memory wall' issue that hinders high-performance computing processors.
Innovation Solution
A memory cell design featuring a write transistor and a read transistor, with optional dummy transistors, utilizing FinFET structures and shared semiconductor fins to enhance operation speed and reduce power consumption, allowing for direct connections between transistors and bit/bit lines without additional devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional DRAM structures are used, then manufacturing is simpler, but access speed is slow and power consumption is high
Solution Approach 1:
The patent merges the write transistor and read transistor into a shared FinFET structure where a single semiconductor fin serves both transistors. This integration reduces the number of separate components while maintaining the functional separation needed for high-speed operation, directly addressing the contradiction between speed and complexity
Solution Approach 2:
The patent transitions from planar transistor structures to vertical FinFET structures, utilizing the third dimension (vertical height of the fin) to increase effective channel area without proportionally increasing footprint. This dimensional change enables faster switching speeds while keeping the memory cell area compact
2Use of energy by moving object
If conventional DRAM structures are used, then device layout is simpler, but power consumption is high
Solution Approach 1:
By combining two separate FinFET structures into a shared structure where one fin serves both write and read transistors, the patent reduces the total number of fins and associated doping regions. This merging decreases the active area requiring power management while maintaining the functional capabilities needed for low-power operation
Solution Approach 2:
The shared semiconductor fin performs multiple functions by serving as the channel for both the write transistor and read transistor. This multi-functionality reduces the overall component count and simplifies the power distribution network, directly addressing the power consumption issue
3Quantity of substance
If additional devices are used for connections, then connectivity is more reliable, but memory density decreases
Solution Approach 1:
The patent merges the connection structures by implementing direct sharing of semiconductor fins between adjacent memory cells. This eliminates the need for additional isolation devices or complex interconnection structures, thereby increasing memory density while maintaining reliable electrical connections through the shared fin structure
Solution Approach 2:
The patent extracts and eliminates unnecessary intermediate connection devices from the memory cell structure. By allowing direct sharing of fins and doping regions between adjacent cells, the design removes redundant components that would otherwise occupy valuable space, thus increasing density
Data Source
AI summary
A device includes a write bit line and a read bit line extending in a first direction, and a write word line and a read word line extending in a second direction perpendicular to the first direction. The device further includes a memory cell including a write transistor and a read transistor. The write transistor includes a first gate connected to the write word line, a first source/drain connected to the write bit line, and a second source/drain connected to a data storage node. The read transistor includes a second gate connected to the data storage node, a third source/drain connected to the read bit line, and a fourth source/drain connected to the read word line.