Latching Circuit Isolation for MTJ Memory
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Solution Overview
Problem
Existing latching circuits face challenges in achieving fast C-Q delay, high process variation tolerance, and low sensing current while avoiding leakage-induced ground boosting and write current degradation, particularly when resistance-based memory elements are not isolated from the latching element during operations.
Innovation Solution
Incorporating an isolation element, such as a transmission gate, to separate resistance-based memory elements from cross-coupled inverters during latching operations, and employing a sensing circuit with feedback paths to reduce sensing current and manage voltage supply effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If resistance-based memory elements are not isolated from the latching element during latching operation, then the circuit structure is simpler, but the C-Q delay increases and process variation tolerance decreases
Solution Approach 1:
The latching circuit is segmented into distinct functional blocks: a latching element (cross-coupled inverters) and resistance-based memory elements (MTJs), connected via an isolation element (transmission gate). This segmentation allows the memory elements to be electrically isolated from the latching element during latching operations, preventing interference and improving C-Q delay and process variation tolerance while maintaining structural organization.
Solution Approach 2:
A transmission gate serves as an intermediary element between the resistance-based memory elements and the latching element. This intermediary controls the electrical connection, enabling isolation during latching operations to improve performance metrics while maintaining a relatively simple overall circuit structure. The transmission gate acts as a switch that mediates the interaction between the two functional blocks.
2Object-affected harmful factors
If resistance-based memory elements are not isolated from the latching element, then fewer components are needed, but leakage current causes ground boosting
Solution Approach 1:
The harmful effect of leakage current is eliminated by extracting the resistance-based memory elements from the direct latching path. The transmission gate isolates the MTJs from the cross-coupled inverters during latching operations, removing the source of leakage-induced ground boosting while maintaining a compact circuit design with minimal additional components.
3Measurement precision
If sensing current is increased to improve sensing accuracy, then measurement precision improves, but power consumption increases
Solution Approach 1:
The sensing circuit performs preliminary actions by pre-charging or pre-biasing circuit nodes before the actual sensing operation. This preliminary preparation reduces the amount of current needed during the sensing phase itself, as the circuit is already in a favorable state for detection, thereby improving sensing accuracy while minimizing power consumption.
Solution Approach 2:
The sensing circuit employs feedback mechanisms where the output of the sensing operation is fed back to adjust or optimize subsequent sensing operations. This feedback allows the circuit to learn from previous operations and reduce the sensing current required while maintaining or improving measurement precision through adaptive optimization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved performance metrics, including faster C-Q delay, increased process variation tolerance, reduced sensing current, and prevention of leakage-induced ground boosting, while maintaining low write current degradation.
Implementation Method 1
A latching circuit includes an isolation element to isolate a pair of cross-coupled inverters from a pair of resistance-based memory elements during a latching operation. The latching circuit may include a pair of magnetic tunnel junction (MTJ) elements
Implementation Method 2
The latching circuit may include a pair of magnetic tunnel junction (MTJ) elements that are isolated from a slave latch element via a transmission gate
Data Source
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AI summary
A non-volatile latch circuit includes a pair of cross-coupled inverters, a pair of resistance-based memory elements, and write circuitry configured to write data to the pair of resistance-based memory elements. The pair of resistance-based memory elements is isolated from the pair of cross-coupled inverters during a latching operation. A sensing circuit includes a first current path that includes a first resistance-based memory element and an output of the sensing circuit. The sensing circuit includes a second current path to reduce current flow through the first resistance-based memory element at a first operating point of the sensing circuit. The sensing circuit may also include an n-type metal-oxide-semiconductor (NMOS) transistor to provide a step down supply voltage to the first current path.