AHB Bus Prefetching Apparatus for Data Transfer Speed
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Solution Overview
Problem
The Advanced High-Performance Bus (AHB) system experiences inefficiencies in data transfer speed due to the time intervals required for data retrieval, necessitating an improvement in data transfer efficiency.
Innovation Solution
The implementation of a prefetching apparatus and method that includes a prefetching address generator, controller, select circuits, and register groups to predict and pre-fetch data addresses and data, optimizing data transfer by matching address and control signals, thereby reducing the time intervals between data requests and responses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional AHB data transfer protocol is used, then system reliability is maintained, but data transfer speed is limited due to time intervals between requests and responses
Solution Approach 1:
The patent implements a prefetching mechanism that performs preliminary data retrieval actions. The prefetching address generator predicts future data addresses needed by the Master, and the prefetching controller initiates data transfer requests in advance before the Master actually needs the data. This preliminary action eliminates waiting time by ensuring data is ready before requested, directly resolving the time interval issue while maintaining AHB protocol reliability.
2Productivity
If prefetching mechanism is implemented, then data transfer efficiency is improved, but device complexity increases due to additional components
Solution Approach 1:
The prefetching apparatus is segmented into distinct functional modules: address storage unit, address generator unit, controller unit, and data buffer units. Each module performs a specific function independently. The address storage stores prefetching addresses, the generator creates address sequences, the controller manages timing and coordination, and buffers hold prefetched data. This segmentation allows the complex prefetching function to be implemented through simple, manageable components, reducing overall system complexity while maintaining high bus efficiency.
3Loss of time
If sequential data transfer is used, then device complexity is minimized, but loss of time increases due to serial data retrieval
Solution Approach 1:
The patent implements continuous useful action through overlapping data transfer operations. While the Master is processing received data, the prefetching controller simultaneously initiates new data transfer requests based on predicted addresses. The data buffer continuously holds prefetched data ready for immediate transfer. This continuous operation eliminates idle time periods between sequential transfers, maintaining constant productive activity on the bus without requiring complex reconfiguration of the transfer mechanism.
Data Source
AI summary
A method for prefetching data in a bus system is provided. First, according to an address signal from a master, a prefetching address generator generates a prefetching address signal and transfers it to a first select circuit. In response to a signal from the master indicates that the address is related to the previous address and the control signal is identical to the previous transfer, or in response to a signal from the master indicates that the address and control signals are unrelated to the previous transfer but is matched to a hit logic, a prefetching controller directs the first select circuit to transfer the prefetching address signal to a slave. And the prefetching controller also directs a second select circuit to transfer the prefetched data which is corresponding to the prefetching address signal from the slave to a master.