Memory Systems TRIZ Cases
- Uni-Directional Bus Ring Controller for Data Streaming
A uni-directional bus ring controller streams data through device modules using serial clocking of address indicator words.
- Host Controller Cache for SATA Command Header Storage
A host controller cache stores command header information to enable efficient switching across multiple SATA devices.
- Non-disruptive Storage Volume Restoration via I/O Freezing
A storage management system freezes input output operations to restore corrupted data while maintaining volume configurations.
- Automated Data Compression Using Idle Counters
Idle counters monitor data inactivity to trigger automatic compression, resolving the trade-off between storage consumption and access speed.
- SSD Controller Throttling Ratio for Garbage Collection
A solid-state memory controller adjusts garbage collection execution frequency using a dynamic throttling ratio derived from invalid page counts.
- Cache Inclusivity Schemes Using Low Priority Evict Operations
Shared cache circuitry converts high-priority eviction messages to lower priorities for outer memory tiers.
- MDIO Control Circuit Broadcast Write Mechanism
A control circuit parses host commands into MDIO signals for broadcast execution across multiple slaves.
- Direct Thread Switching Bypassing Run Queue
A direct thread switching mechanism bypasses the run queue to place woken-up threads immediately onto available resources.
- Pattern Language Surrogate Context Look-up
A pattern language uses surrogate and extends relationships to define class fields within ontological contexts.
- Dynamic Write Cache Voltage Monitoring
A storage interface controller adjusts write cache size based on real-time voltage supply levels.
- Interface Circuit Noise Detection via Signal Comparison
An interface circuit compares logic level changes in access signals to detect noise without adding parity bits.
- Cache Memory Dual Scheduling for Full-Duplex Throughput
Segmenting the cache scheduler into independent queues resolves full-duplex complexity while boosting bandwidth throughput.
- L1 Cache Deferral Mechanism for Shared Memory Arbitration
A level one cache defers client requests to shared storage when entries are unavailable, replaying them upon data availability.
- Java Classpath Matching via Hash Code Cache
A cooperative class cache system identifies and records matching classpaths using unique keys generated from classloader IDs.
- Multi-Level Address Table for Solid-State Storage
Segmenting the address table into volatile and non-volatile storage reduces memory requirements while maintaining performance.
- I/O Control Device Logical Address Conversion
Input output control device converts logical addresses to local device addresses via a PCIe switch for efficient instruction routing.
- Firmware Update Logical Address Remapping
A memory mapper converts logical addresses to physical ones during firmware updates.
- Parallel Execution Environment for Technical Computing Programs
A parallel execution environment manages technical computing programs across multiple nodes.
- Static Partition Scheduling Timeline for Avionics Context Switch Reduction
A static partition scheduling timeline merges adjacent time slices to minimize context switching overhead in ARINC-653 avionics systems.
- Cache Memory Dirty Bit Transfer for Eviction Reduction
A cache hierarchy passes dirty value indications during line eviction to maintain accurate status across memory levels.
- Memory Controller OS Recognition via Handshaking
An intermediary driver recognizes operating systems via handshaking patterns to bypass OS restrictions on mass storage commands.
- RAM Disk Boot Image for Non-Intrusive IT Endpoint Imaging
A boot image instantiates a RAM disk on managed endpoints to harvest local disk data without locking the drive.
- Business Object Templates for Data Consolidation
Hierarchical business object templates enable data consolidation and reuse by projecting entities into specific structures, reducing modeling redundancies.
- Speculative Compilation for Incremental Source Code Processing
Speculative compilation compiles source code portions during editing via waypoints, resolving idle time waste while maintaining optimization efficiency.
- Multiprocessor Cache Coherency with Victim Cache Integration
A multiprocessor cache coherency system integrates victim caches to manage data blocks across processing units.
- SSD Controller with Parallel Channels for MLC Error Correction
Parallel flash channels with independent controllers resolve bit error rate trade-offs in multi-level cell memory while sustaining high throughput.
- Non-volatile Memory Block Wear-Leveling via Read Count Monitoring
A non-volatile memory controller tracks read status to replace worn data blocks with spare units.
- Formatted Matrix Data Structure for Sparse Vector Multiplication
A formatted matrix data structure partitions sparse matrices into tiles to store non-zero values in packets, enabling efficient vector multiplication across hardware platforms.
- Globally Incremented Variable for Parallel Transaction Integrity
A globally incremented variable tracks shared data changes to enable parallel transaction execution.
- AHB Bus Prefetching Apparatus for Data Transfer Speed
A prefetching apparatus predicts data addresses and pre-fetches data to reduce retrieval latency in Advanced High-Performance Bus systems.
- Peripheral Device Microcontroller Emulating Memory Controller
A peripheral microcontroller retrieves basic device information from general-purpose memory and formats it for standard computing system requests.