Multiprocessor Cache Coherency with Victim Cache Integration

The patent introduces a victim cache as an intermediary buffer between the L2 cache and main memory. When cache lines need to be evicted, they are first placed in the victim cache rather than directly to memory, reducing bandwidth consumption. The victim cache acts as a temporary holding area that can be later cleaned to main memory in bulk operations, thereby mediating between the need for cache space and the desire to minimize bandwidth usage.

The patent merges the victim cache functionality with the existing L2 cache structure. Instead of adding completely separate dedicated victim caches for each L2 cache, the system shares victim cache resources across multiple L2 caches. This combining approach provides the necessary cache line management capabilities while reducing the total hardware area and power consumption compared to having dedicated victim caches for each L2 cache.

The patent implements feedback mechanisms through coherency protocols that track the history and state of cache lines. When a cache line is evicted from one L2 cache to another via the shared L3 cache, the system monitors and records this movement. The feedback from these tracking mechanisms allows the system to detect when cache lines are circulating and take corrective actions, such as preventing further circulation or triggering write-backs to main memory, thereby maintaining coherency while enabling cache sharing.

The patent applies partial action by selectively accepting cache lines in the victim cache based on specific criteria rather than unconditionally accepting all incoming lines. The system evaluates factors such as the state of existing cache lines, access patterns, and coherency requirements before accepting new lines. This selective approach allows the victim cache to utilize available space while avoiding unnecessary evictions of important cache lines, thereby optimizing both cache utilization and energy efficiency.