Multi-Level Address Table for Solid-State Storage
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Solution Overview
Problem
As solid-state storage devices increase in capacity, they face challenges in maintaining large address tables due to design, cost, and power constraints associated with volatile memory, limiting performance and efficiency.
Innovation Solution
A multi-level addressing system is implemented in solid-state storage devices, where a first level of the address table is stored in volatile memory and second and third levels are stored in flash memory devices, using a controller to determine parameters from logical addresses to map them to physical addresses through a three-level address table structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If large amounts of volatile memory are used to store address tables, then performance in referencing and maintaining address tables is improved, but design complexity, cost, and power consumption increase
Solution Approach 1:
The address table is divided into multiple levels (first level in volatile memory, second and third levels in flash memory devices), allowing the system to maintain performance for frequently accessed address information while storing less frequently accessed address mappings in non-volatile memory, thereby reducing overall volatile memory requirements and design complexity
Solution Approach 2:
The patent transitions from a single-level address table structure to a multi-level hierarchical structure, adding dimensional organization to the address mapping system. This allows efficient caching of frequently accessed address translations in volatile memory while persisting less frequently accessed mappings in flash memory
2Productivity
If large amounts of volatile memory are used to store address tables, then performance in referencing and maintaining address tables is improved, but cost increases
Solution Approach 1:
The address table storage is segmented between volatile memory (for performance-critical portions) and flash memory devices (for capacity-critical portions), allowing optimization of cost by using cheaper non-volatile memory for the bulk of address mappings while maintaining performance with a smaller amount of expensive volatile memory
Solution Approach 2:
The patent changes the storage parameter (memory type) based on the access frequency and importance of different address table portions, using volatile memory for hot data and flash memory for cold data, thereby optimizing the cost-performance tradeoff
3Productivity
If large amounts of volatile memory are used to store address tables, then performance in referencing and maintaining address tables is improved, but power consumption increases
Solution Approach 1:
The address table is segmented into volatile and non-volatile storage portions, allowing the system to maintain only essential address mappings in power-consuming volatile memory while storing less frequently accessed mappings in power-efficient flash memory, thereby reducing overall power consumption
Solution Approach 2:
The system periodically updates and synchronizes address tables between volatile and flash memory, maintaining performance through volatile memory caching while using flash memory for persistent storage, thereby reducing the amount of volatile memory needed and associated power consumption
Data Source
AI summary
A solid-state storage device with multi-level addressing is provided. The solid-state storage device includes a plurality of flash memory devices, a volatile memory, and a controller. The controller is configured to store data received from a host in the plurality of flash memory devices in response to a write command and to read the data stored in the plurality of flash memory devices in response to a read command. The controller is further configured to maintain a multi-level address table that maps logical addresses received from the host identifying the data stored in the plurality of flash memory devices to physical addresses in the plurality of flash memory devices containing the data. A first level of the multi-level address table is maintained by the controller in the volatile memory and second and third levels of the multi-level address table are maintained by the controller in the plurality of flash memory devices.