Uni-Directional Bus Ring Controller for Data Streaming
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Solution Overview
Problem
Current digital data streaming technologies face inefficiencies in managing dynamic data streams across multiple device modules, particularly in determining binary addresses and executing read/write operations in a unified and efficient manner within a stream ring configuration.
Innovation Solution
The implementation of a uni-directional bus system with hardware-compiled device modules, where each module analyzes binary addresses and executes operation instructions to either read or write data streams, ensuring data is processed and streamed through a ring controller without returning until all modules are traversed, utilizing a specific bus wire set for serial clocking of operation and address indicator words.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a traditional multi-master bus system is used, then device modules can independently control data streams, but address determination and operation execution become complex and inefficient
Solution Approach 1:
The system divides the bus into unidirectional segments with single-master control. Each device module has a dedicated control signal line (e.g., ENA, ENB, ENC) that segments the control function, allowing only one module to initiate operations at a time while simplifying address determination through sequential scanning of control signals.
Solution Approach 2:
The patent introduces control signal lines as intermediaries between device modules and the data stream. These control signals (ENA, ENB, ENC) mediate the interaction by indicating which module should be active, thereby simplifying the complexity of direct address determination and operation execution.
2Productivity
If data streams are managed across multiple device modules, then data processing capability increases, but redundant data transfer occurs
Solution Approach 1:
The system implements feedback through control signal lines that indicate the active state of each device module. When a module's control signal is high (e.g., ENA=1), it signals that the module is ready to receive or process data, preventing redundant transfers by ensuring data is only sent to the currently active module.
Solution Approach 2:
The control signal lines dynamically change states based on which device module should process the data. This dynamic control (ENA=1/0, ENB=0/1, ENC=0/1) enables efficient data routing to the appropriate module without redundant transfers, adapting the data stream direction in real-time.
3Device complexity
If a unidirectional bus system is implemented, then data streaming coordination is simplified, but device modules must traverse the entire ring
Solution Approach 1:
The system performs preliminary action by pre-configuring control signal lines for each device module before data streaming begins. This preliminary setup (establishing ENA, ENB, ENC control lines) simplifies coordination during operation, as modules only need to respond to control signals rather than complex real-time negotiation.
Solution Approach 2:
The unidirectional bus maintains continuous data flow through the ring in a coordinated manner. Once a module is activated by its control signal, it continuously processes data until completion, ensuring useful action continues without interruption while the control signals coordinate the traversal efficiently.
Data Source
AI summary
Systems and methods for streaming data. Systems allow read/write across multiple or N device modules. Device modules on a bus ring configure at power up (during initialization process); this process informs each device module of its associated address values. Each ringed device module analyzes an address indicator word, which identifies an address at which a read/write operation is intended for, and compares the address designated by the address indicator word to its assigned addresses; when the address designated by the address indicator word is an address associated with the device module, the device module read/writes from/to the address designated by the address indicator word. Memory controller (ring controller or master bus) is not required to ‘know’ which memory chip/device module in a daisy chain the address command word is intended for. Therefore, system embodiments allow streaming without consideration of a number of memory chips/device modules on bus. The bus isolates modules like object oriented programming.