Cache Inclusivity Schemes Using Low Priority Evict Operations
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Solution Overview
Problem
Existing cache architectures face challenges in supporting multiple cache inclusivity schemes concurrently due to conflicts between eviction and probe operations, leading to potential concurrency issues and data hazards.
Innovation Solution
The implementation of an agent with circuitry that enables two types of eviction messages at different priorities, allowing for concurrent support of multiple cache inclusivity schemes by converting high-priority eviction messages to low-priority messages and maintaining a data storage that is inclusive of cache blocks being evicted.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high-priority eviction messages are used to maintain cache inclusivity, then cache coherence is maintained, but probe operations are blocked causing performance degradation
Solution Approach 1:
The patent implements dynamic priority adjustment for eviction messages based on the target cache's inclusivity scheme. The shared cache determines whether to forward high-priority or low-priority eviction messages to outer caches, dynamically adapting the eviction message priority to match the target cache's capabilities and requirements.
Solution Approach 2:
The patent changes the priority parameter of eviction messages during transmission through the cache hierarchy. High-priority eviction messages from inner caches are converted to low-priority messages when forwarded to outer caches that do not require high-priority eviction, thereby resolving the contradiction between maintaining coherence and allowing probe operations to proceed.
2Adaptability or versatility
If multiple cache inclusivity schemes are supported concurrently, then system versatility is improved, but circuit complexity increases
Solution Approach 1:
The shared cache is designed with universal functionality to handle multiple cache inclusivity schemes (inclusive, exclusive, and non-inclusive) simultaneously. It can selectively forward high-priority or low-priority eviction messages based on the target cache's type, making a single cache design adaptable to various inclusivity requirements without requiring separate dedicated circuits for each scheme.
Solution Approach 2:
The shared cache acts as an intermediary between inner caches and outer caches with different inclusivity schemes. It receives high-priority eviction messages from inner caches and intelligently converts them to appropriate priority levels for outer caches, mediating the interaction between different inclusivity schemes and simplifying the overall system complexity.
3Speed
If high-priority eviction messages are transmitted throughout the cache hierarchy, then eviction speed is improved, but power consumption increases
Solution Approach 1:
The patent applies local quality by transmitting high-priority eviction messages only to caches that require them (inner caches with inclusive schemes) and converting to low-priority messages when forwarding to caches that do not require high-priority eviction (outer caches with exclusive or non-inclusive schemes). This localized approach to message priority reduces unnecessary power consumption while maintaining eviction speed where needed.
Data Source
AI summary
Systems and methods are disclosed for concurrent support for multiple cache inclusivity schemes using low priority evict operations. For example, some methods may include, receiving a first eviction message having a lower priority than probe messages from a first inner cache; receiving a second eviction message having a higher priority than probe messages from a second inner cache; transmitting a third eviction message, determined based on the first eviction message, having the lower priority than probe messages to a circuitry that is closer to memory in a cache hierarchy; and, transmitting a fourth eviction message, determined based on the second eviction message, having the lower priority than probe messages to the circuitry that is closer to memory in the cache hierarchy.