Cache Memory Dual Scheduling for Full-Duplex Throughput
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Solution Overview
Problem
Existing cache memory devices face increased complexity and reduced efficiency when implementing full-duplex designs due to the need to process read and write commands simultaneously, leading to potential degradation of cache scheduler performance and bandwidth throughput.
Innovation Solution
A dual scheduling mechanism using two or more cache schedulers with even-odd classification of commands based on their addresses, allowing simultaneous processing of read and write commands through separate scheduling queues and cache tags, reducing complexity and enhancing bandwidth throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a full-duplex design is applied to the cache to process read and write commands simultaneously, then bandwidth throughput is improved, but device complexity increases
Solution Approach 1:
The cache scheduler is segmented into multiple independent schedulers (first cache scheduler and second cache scheduler), each handling different types of commands. The first cache scheduler processes read commands while the second cache scheduler processes write commands, allowing simultaneous operation without mutual interference, thus achieving full-duplex functionality while maintaining manageable complexity in each individual scheduler
Solution Approach 2:
The patent introduces a new dimension of command classification by separating the scheduling space into multiple independent scheduling dimensions. Each cache scheduler operates in its own scheduling dimension, processing commands independently, which enables simultaneous read and write operations without the complexity of coordinating a single scheduler for all command types
2Speed
If a full-duplex design is applied to the cache to process read and write commands simultaneously, then data transfer speed is improved, but ease of operation deteriorates
Solution Approach 1:
By segmenting the cache scheduler into multiple independent schedulers, each responsible for specific command types, the system achieves simultaneous read and write processing (improving data transfer speed) while maintaining simple, dedicated operation logic in each scheduler (preserving ease of operation)
Solution Approach 2:
Each cache scheduler is designed to autonomously manage its own command queue and scheduling decisions without requiring complex coordination with other schedulers. The first cache scheduler independently manages read commands while the second independently manages write commands, enabling self-service operation that simplifies the overall system operation despite full-duplex functionality
Data Source
AI summary
Provided is a cache memory device including a command reception unit for packetizing each of read commands and write commands and classifying them as even or odd; a cache scheduler comprising a first reorder scheduling queue for receiving commands classified as even numbers from the command reception unit and scheduling the commands classified as even numbers for cache memory accesses and a second reorder scheduling queue for receiving commands classified as odd numbers from the command reception unit and scheduling the commands classified as odd numbers for cache memory accesses; and an access execution unit for performing cache memory accesses via a cache tag to scheduled commands classified as even numbers and scheduled commands classified as odd numbers.