Cache Memory Dirty Bit Transfer for Eviction Reduction
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Solution Overview
Problem
Exclusive cache systems in data processing apparatuses experience increased evictions, leading to performance adverse effects, particularly when evicting cache lines to main memory, as they typically mark all evicted cache lines as dirty, resulting in unnecessary evictions and latency.
Innovation Solution
Implementing a data processing apparatus with a hierarchy of cache memories where the n-th level cache memory passes an indication of associated dirty values to the n+1-th level cache memory upon eviction, ensuring only modified cache lines are marked as dirty, thereby reducing unnecessary evictions and latency by maintaining accurate dirty/clean status during linefill processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If exclusive cache behaviour is employed to increase effective cache size, then cache hit rate is improved, but the number of evictions increases causing performance degradation
Solution Approach 1:
The patent changes the state parameter of cache lines by accurately tracking their dirty/clean status. When a cache line is evicted from L1 to L2 cache, the dirty bit information is preserved and transferred to L2 cache. This parameter change allows the system to distinguish between modified and unmodified cache lines, enabling selective eviction only when necessary, thus reducing unnecessary evictions while maintaining the benefits of exclusive cache behavior.
2Reliability
If all evicted cache lines are marked as dirty in exclusive cache systems, then data consistency is maintained, but unnecessary evictions to main memory occur increasing latency
Solution Approach 1:
The patent extracts the dirty bit information from the eviction process and transfers it separately to the L2 cache. This extraction allows the system to identify which cache lines are actually dirty and only evict those to main memory, while clean cache lines can be discarded without writing back to main memory. This resolves the contradiction by maintaining data consistency for dirty lines while avoiding unnecessary latency for clean lines.
Solution Approach 2:
The patent implements a feedback mechanism where the dirty bit status is tracked and fed back through the cache hierarchy. When a cache line is evicted from L1 to L2, the dirty bit information is passed along. This feedback enables L2 cache and subsequent levels to make informed decisions about whether to write back to main memory, thus maintaining data consistency while minimizing unnecessary memory operations and latency.
Data Source
AI summary
The present invention provides a data processing apparatus and method for managing cache memories. The data processing apparatus comprises a processing unit for issuing an access request seeking access to a data value, and a hierarchy of cache memories for storing data values for access by the processing unit. The hierarchy of cache memories comprises at least an n-th level cache memory and n+1-th level cache memory which at least in part employ exclusive behavior with respect to each other. Each cache memory comprises a plurality of cache lines, at least one dirty value being associated with each cache line, and each dirty value being settable to indicate that at least one data value held in the associated cache line is more up-to-date than a corresponding data value stored in a main memory. When employing exclusive behavior, the n-th level cache memory is operable, on eviction of a cache line from the n-th level cache memory to the n+1-th level cache memory, to additionally pass an indication of the at least one associated dirty value from the n-th level cache memory to the n+1-th level cache memory. This has been found to reduce the frequency of evictions of lines from the n+1-th level cache memory when employing exclusive behaviour.