AI Chip Parallel Operation Circuits Power Reduction
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Solution Overview
Problem
Existing artificial intelligence (AI) chips face challenges in efficiently executing multiple operations in parallel while minimizing power consumption.
Innovation Solution
The proposed AI chip incorporates a design with multiple operation circuits and data allocators that allow for parallel execution of operations, including convolution and activation functions, with shared operation circuits to reduce power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple operation circuits are used to execute operations in parallel, then computational productivity is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent implements operation circuit sharing where a single operation circuit can be dynamically allocated to different neural network layers. The operation circuit is configured to execute operations for multiple layers sequentially, controlled by layer selection signals. This allows one physical circuit to serve multiple logical functions, reducing the total number of circuits needed while maintaining parallel processing capability across different layers.
Solution Approach 2:
The patent introduces dynamic resource allocation mechanisms where operation circuits can be dynamically assigned to different layers based on computational requirements. The system uses configurable parameters and control signals to dynamically route data and operations, allowing the architecture to adapt between parallel execution modes and sequential sharing modes, optimizing the balance between throughput and resource utilization.
2Productivity
If multiple operation circuits are used to execute operations in parallel, then computational productivity is improved, but power consumption increases
Solution Approach 1:
The operation circuit is designed to be multi-functional, serving multiple neural network layers through dynamic configuration. By reusing the same physical circuit for different layers rather than dedicating separate circuits to each layer, the patent significantly reduces the total power consumption while maintaining the ability to process multiple layers in parallel through time-multiplexed execution.
Solution Approach 2:
The patent implements a resource recovery mechanism where the operation circuit completes execution for one layer, then transitions to serve the next layer. This allows efficient recovery and reuse of the same computational resources, avoiding the continuous power consumption that would result from having permanently active parallel circuits for all layers simultaneously.
3Use of energy by moving object
If operation circuits are shared among multiple layers, then power consumption is reduced, but execution time for each layer increases
Solution Approach 1:
The patent employs dynamic scheduling and configuration mechanisms that allow the operation circuit to be efficiently allocated to different layers. Through optimized control signals and data routing, the system minimizes transition overhead between layers and maximizes the utilization of the shared circuit, reducing the time penalty associated with resource sharing while maintaining lower power consumption compared to dedicated parallel circuits.
Data Source
AI summary
The present disclosure provides an artificial intelligence chip, an accelerator and an operation method, relating to the technical field of artificial intelligence, the chip comprising: a first operation circuit configured to execute a first operation to output a first operation result; a second operation circuit connected in parallel with the first operation circuit and configured to execute a second operation identical to the first operation to output a second operation result; and a third operation circuit configured to, upon receiving the first operation result and the second operation result, execute a third operation different from the first operation on the first operation result and the second operation result, respectively, to output a third operation result, respectively.