Air Gap Formation in Semiconductor Device for Parasitic Capacitance Reduction
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Solution Overview
Problem
As semiconductor processing sizes decrease and capacitance requirements increase, the parasitic capacitance between bit lines and capacitor contacts in DRAMs grows, reducing signal amplification due to shorter distances and longer bit lines.
Innovation Solution
A semiconductor device manufacturing method that forms a trench in a dielectric layer between conductive structures, lines the trench with a material, and then removes the material to create an air gap between the conductive plug and the dielectric layer, reducing parasitic capacitance by using a low dielectric constant air gap.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If processing sizes are decreased to increase device density, then device integration is improved, but parasitic capacitance between bit lines and capacitor contacts increases due to shorter distances
Solution Approach 1:
The patent introduces an air gap as an intermediary layer between the bit line and capacitor contact. This air gap acts as a mediator that reduces the parasitic capacitance coupling between these two conductive structures, allowing high device integration while minimizing the harmful capacitive effect.
Solution Approach 2:
The patent changes the dielectric parameter by replacing the traditional dielectric material with an air gap (which has a dielectric constant of approximately 1.0). This parameter change significantly reduces the parasitic capacitance while maintaining the compact structure needed for high device integration.
2Reliability
If capacitance requirements are increased to improve memory performance, then signal amplification is improved, but parasitic capacitance increases due to longer bit lines
Solution Approach 1:
The air gap serves as an intermediary that decouples the parasitic capacitance between the extended bit lines and capacitor contacts. This allows the bit lines to be made longer to meet increased capacitance requirements while the air gap mediates to prevent excessive parasitic capacitance from degrading signal amplification.
3Area of stationary object
If distance between bit lines and capacitor contacts is decreased to increase device density, then device integration is improved, but parasitic capacitance increases
Solution Approach 1:
The air gap is positioned as an intermediary layer in the vertical direction between the bit line and capacitor contact, allowing horizontal proximity for high device density while maintaining vertical separation to reduce parasitic capacitance.
Solution Approach 2:
The patent resolves the density-capacitance contradiction by moving the separation mechanism to the vertical dimension (using an air gap between layers) rather than increasing horizontal distance, thus maintaining high device density while reducing parasitic capacitance.
4Reliability
If bit line length is increased to meet capacitance requirements, then memory performance is improved, but parasitic capacitance increases
Solution Approach 1:
The air gap acts as a mediator that allows bit lines to be extended for increased memory capacitance while preventing the proportional increase in parasitic capacitance, thus maintaining memory performance without excessive parasitic effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Effectively reduces parasitic capacitance by lowering the equivalent dielectric constant between conductive structures, enhancing signal amplification in DRAMs without requiring additional device volume or components.
Implementation Method 1
reducing parasitic capacitance by using a low dielectric constant air gap
Data Source
AI summary
A semiconductor device and a manufacturing method of the same are provided. The method includes forming a plurality of first conductive structures and a first dielectric layer between the first conductive structures on a substrate. The method also includes forming a trench between the first dielectric layer and the first conductive structures. The method further includes forming a liner material on a sidewall and a bottom of the trench. In addition, the method includes forming a conductive plug on the liner material in the trench. The method also includes removing the liner material to form an air gap, and the air gap is located between the conductive plug and the first dielectric layer.