Transistor TRIZ Cases

A semiconductor device integrates a metal-insulator-metal capacitor and thin film resistor using shared conductive materials in the back end of line.

A gated microelectronic device uses a single dopant type across source, channel, and drain regions to control charge carrier accumulation.

A voltage supply device generates multiple levels using medium voltage MOS transistors.

A semiconductor device manufacturing method creates an air gap between conductive structures to lower the equivalent dielectric constant.

Self-aligned via structures enable vertical electrical connections through transistor layers without expanding the device footprint.

Fabricating sidewall recesses on semiconductor fins reduces off-state leakage current and improves yield in fin field effect transistor manufacturing.

A pixel driving circuit uses an N-type storage transistor to minimize leakage current in OLED displays.

A TFT-LCD array substrate uses a second insulating layer to expose source, drain, and channel regions through an opening.

A semiconductor device with an SOI substrate uses a thyristor to create a discharge route for electrostatic surge.

Segmented etching sequences form via structures in dense and isolated regions, preventing punch-through while maintaining manufacturing precision.

Grinding a thick CZ substrate creates a stable field stop layer, preventing wafer breakage during ion implantation and reducing saturation collector voltage.

Air gaps between adjacent memory cell strings reduce parasitic capacitance, improving signal transmission reliability in vertical non-volatile memory devices.

A trench-based metal-insulator-metal capacitor structure stacks nested dielectric layers and conductive plates to increase capacitance density.

Composite silicide regions resolve resistivity roll-off and thermal sensitivity contradictions in deep-submicron MOS devices.

A semiconductor device adjusts gate voltage to limit current-carrying capability during motor operation.

Thicker sacrificial nanosheets convert to dielectric oxide, isolating nFET and pFET channels to resolve punch-through leakage.

Heat treatment forms a manganese oxide layer on copper alloy electrodes, preventing oxidation and maintaining low resistance while securing adhesiveness.

Graded film density in the channel protective layer of an oxide semiconductor thin film transistor prevents peeling caused by high stress.

Replaces parasitic PN body diodes with integrated Schottky rectifiers to eliminate carrier recombination delays and boost operational efficiency.

Stacked protective layers cover conductive wiring surfaces to prevent low-resistance material diffusion into the semiconductor substrate.

A semiconductor layout uses a diode and MOS transistor to discharge electric charges from the well.

A semiconductor circuit arrangement uses series-connected transistors to lower on-resistance while maintaining voltage blocking capability.

Code division multiplexing drive circuit selects and combines signals from multiple detection electrodes to increase output intensity.

Angled ion implantation creates variable oxide thicknesses, eliminating dummy fins to reduce SRAM cell size at 10 nm nodes.

Merging source, well, and field plate connections reduces signal ports while the field plate disperses electric fields to prevent breakdown.

A tensile hard mask layer counters compressive stress to minimize buckling and maintain surface planarity in semiconductor substrates.

An imaging device uses an asymmetric auxiliary electrode to control signal charge trapping regions within a photoelectric conversion layer.

A control circuit detects noise signals during switch state changes to modulate driver current.

An aluminum oxynitride memristor resolves CMOS compatibility constraints while maintaining reliable resistive switching behavior.

A semiconductor fin epitaxy structure forms a groove with a specific curvature radius to expand source drain contact area.

Dual-plane fan-out structure doubles input output connections on a three dimensional integrated circuit package while maintaining compact footprint.

Solution processed metal oxide thin film transistors reduce charge loss by matching first and second metal oxide compositions.

A doped well trapping layer electrically isolates semiconductor fins from the bulk substrate.

Integrated solid-state energy source enables autonomous operation without external power connections.

A sub-fin passivation layer applied to replacement channel fins in FinFET structures.

Zn-In-Hf oxide semiconductor channels achieve poly-Si level mobility while maintaining low-temperature manufacturing simplicity.

Metal dams separate gate electrodes to suppress boundary effects and maintain threshold voltage control during high-density integration.

Two-masking step process creates right-angle STI corners to eliminate line-end rounding and reduce control gate spacing in split gate flash memory arrays.

A wafer-level chip-scale package uses a common drain electrode to form a low-resistance current path between semiconductor devices.

A transistor structure uses a polysilicon interconnection layer between silicon carbide and gallium nitride layers.

A flexible display manufacturing method uses lyophilic grooves to capture ink droplets precisely between lyophobic partition walls.

Varying boron density in the mask layer prevents shoulder drops and preserves hole precision during high aspect ratio etching.

A semiconductor manufacturing method adjusts first insulation film thickness and heat treatment temperature to control oxygen diffusion into the oxide semiconductor layer.

A FinFET spacer formation process deposits conformal materials and uses tilted ion implantation to define precise gate sidewall structures.

A semiconductor pillar connects thin fins to a contact plug, enabling uniform electrical connection without damaging delicate fin structures.

A polycrystalline silicon layer forms without photomasks using the gate electrode as a shadow mask.

A bias circuit reduces control voltage requirements in an overcurrent protective device using a field-effect transistor switch.

Inserting a metal oxide layer between the high-K dielectric and metal gate reduces junction leakage and Vt variability without high channel doping.

A thin film transistor substrate aligns channel lengths with laser scanning directions to maintain high carrier mobility in specific areas.

A transistor structure uses an asymmetric sidewall spacer to define control terminal width and field plate position within a trench.