FinFET Fabrication Recesses Reduce Leakage Current
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Solution Overview
Problem
The fabrication of FinFETs faces yield loss issues due to significant leakage current (Ioff) resulting from unstable processes and a limited process window, which affects the reliability and efficiency of the devices.
Innovation Solution
A method for fabricating FinFETs involving the formation of trenches and semiconductor fins, followed by the creation of insulating structures and recesses on the fin sidewalls, and the partial coverage of the fins with a gate stack, which reduces leakage current and improves yield and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If conventional FinFET fabrication process is used, then device scaling is achieved, but leakage current increases and yield decreases
Solution Approach 1:
The patent applies local quality by forming recesses at specific locations on the fin structure (source/drain regions) while maintaining the overall fin geometry. This localized modification reduces leakage current at critical areas without affecting the entire fin structure, thereby improving reliability while preserving device scaling benefits
Solution Approach 2:
The recess formation is performed as a preliminary step before final gate fabrication and contact formation. By pre-modifying the fin structure to reduce leakage, the subsequent fabrication steps can proceed with better process margin and higher yield, addressing the reliability issue before it propagates through the manufacturing process
2Ease of manufacture
If conventional FinFET fabrication process is used, then manufacturing is simplified, but process stability decreases and yield is lost
Solution Approach 1:
The fabrication process is segmented into distinct stages: fin formation, recess formation, gate fabrication, and contact formation. This segmentation allows each step to be optimized and controlled independently, improving process stability without significantly increasing overall manufacturing complexity. The recess formation step is inserted at a point where it can be performed with standard lithography and etching tools
3Productivity
If conventional FinFET fabrication process is used, then production efficiency is maintained, but leakage current causes yield loss
Solution Approach 1:
The patent extracts the problematic high-leakage regions by forming recesses that remove excess semiconductor material from the source/drain areas. This extraction of material at critical locations directly reduces leakage current while the overall fabrication flow maintains production efficiency by using standard processing steps that can be performed at existing manufacturing rates
Data Source
AI summary
A method for fabricating a fin field effect transistor (FinFET) is provided. The method includes: patterning a substrate to form a plurality of trenches in the substrate and at least one semiconductor fin between the trenches; forming a plurality of insulators in the trenches; forming a patterned photoresist on the insulators, wherein sidewalls of the semiconductor fin are partially covered by the patterned photoresist, and at least one area of the sidewalls is exposed by the patterned photoresist; by using the patterned photoresist as a mask, partially removing the semiconductor fin from the at least one area of the sidewalls exposed by the patterned photoresist so as to form at least one recess on the sidewalls of the semiconductor fin; removing the patterned photoresist after forming the at least one recess; and forming a gate stack to partially cover the semiconductor fin and the insulators.