SOI Semiconductor ESD Protection via Thyristor Segmentation
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Solution Overview
Problem
Semiconductor devices with SOI substrates face low damage resistance against electrostatic surges due to the presence of compound parasitic diodes with bidirectional polarity, which reduces their effectiveness in discharging electrostatic discharge (ESD) when the surge is applied in the opposite direction.
Innovation Solution
The semiconductor device incorporates a p-type and n-type field effect transistor with parasitic diodes and an inter-power-supply protection circuit, including capacitors, to create a discharge route that avoids backward operation parasitic diodes, ensuring efficient ESD protection by connecting the output terminal to voltage sources through parallel parasitic diodes with simplex polarity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If an FD type SOI-MOS transistor is used to achieve lower power consumption and miniaturization, then power consumption is reduced and device size is minimized, but damage resistance against electrostatic surge is significantly reduced due to compound parasitic diodes with bidirectional polarity
Solution Approach 1:
The invention segments the ESD protection function by introducing a dedicated protection element (thyristor) separate from the FD SOI-MOS transistor. The thyristor is configured with specific diffusion layers (first and second diffusion layers of first conductivity type, third and fourth diffusion layers of second conductivity type) that create simplex polarity parasitic diodes, dividing the protection mechanism from the main transistor structure.
Solution Approach 2:
The invention introduces a thyristor as an intermediary protection element between the FD SOI-MOS transistor and the external environment. This thyristor acts as a mediator that handles ESD protection through its simplex polarity parasitic diodes, preventing direct exposure of the transistor to electrostatic surge and avoiding the compound parasitic diode problem inherent in FD SOI-MOS structures.
2Reliability
If a thyristor type protection element is added to discharge electrostatic surge, then ESD protection function is provided, but device structure becomes more complex
Solution Approach 1:
The invention merges the thyristor protection element with the FD SOI-MOS transistor structure by integrating the diffusion layers of the thyristor with the transistor's diffusion layers. The first and second diffusion layers serve dual purposes as both transistor components and thyristor components, reducing the need for separate structures and minimizing overall device complexity while maintaining ESD protection functionality.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the device's resistance to electrostatic discharge damage by allowing efficient discharge of ESD in both forward and reverse polarities, improving overall ESD protection without relying on backward operation parasitic diodes.
Implementation Method 1
the electrostatic surge applied to a drain through an output terminal will be discharged to the power source through a well-electric supply terminal due to forward operation of the parasitic diode
Implementation Method 2
an inter-power-supply protection circuit, including capacitors, to create a discharge route
Data Source
AI summary
A semiconductor device with an ESD protection function has an SOI substrate, first to fourth diffusion layers, and a gate. The SOI substrate has a semiconductor layer on an insulation layer. The first diffusion layer is of a first conductivity type and is formed on the semiconductor layer. The second diffusion layer is of the first conductivity type and is formed on the semiconductor layer. The third diffusion layer is of a second conductivity type and is formed on the semiconductor layer so as to be adjacent to the first and second diffusion layers. The fourth diffusion layer is of the second conductivity type and is formed on the semiconductor layer so as to be adjacent to the first diffusion layer and electrically connected to the second diffusion layer. The gate is formed over the third diffusion layer.