Trench MIM Capacitor Structure for High Density IC Design
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Solution Overview
Problem
The increasing complexity and miniaturization of integrated circuits (ICs) lead to limited capacitance in traditional capacitor structures, hindering the performance and functionality of electrical products.
Innovation Solution
The design incorporates a first metal-insulator-metal (MIM) capacitor with a bottom plate, patterned dielectric layers, and a medium plate formed in a trench, along with a second MIM capacitor formed on top, enhancing capacitance and density by sharing the medium plate and electrically connecting the bottom and top plates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If traditional capacitor structures are used in inter-metal dielectric layers, then the IC design is simpler, but the capacitance is limited due to miniaturization and increased complexity of IC devices
Solution Approach 1:
The patent transitions from planar capacitor structures to three-dimensional trench-based MIM capacitor structures. By forming capacitors vertically within trenches etched into the substrate, the design utilizes the third dimension (depth) to increase capacitance without consuming additional lateral area, directly resolving the contradiction between limited capacitance and limited space
Solution Approach 2:
The patent implements nested capacitor structures where multiple dielectric layers and conductive plates are stacked vertically within the same trench footprint. The first and second patterned dielectric layers are positioned at different depths, creating a nested configuration that maximizes capacitance density by effectively nesting capacitor elements within the available vertical space
2Adaptability or versatility
If IC devices are miniaturized and complexity increases, then more functions are achieved, but the space for capacitor structures becomes smaller
Solution Approach 1:
As IC complexity and functionality increase, lateral space becomes increasingly constrained. The patent responds by moving capacitor formation into the vertical dimension through trench structures, allowing multiple capacitor elements to be stacked within the same planar footprint, thereby maintaining capacitor space availability even as lateral area is consumed by additional IC functions
3Quantity of substance
If traditional capacitor structures are used, then manufacturing process is simpler, but capacitance density is limited
Solution Approach 1:
The patent employs nested dielectric layers (first and second patterned dielectric layers) and multiple conductive plates (bottom plate, medium plate, top plate) within the same horizontal footprint. This nesting arrangement increases capacitance density by effectively multiplying the dielectric volume without proportionally increasing the device footprint, accepting increased structural complexity as necessary to achieve higher capacitance density
Data Source
AI summary
An integrated circuit includes a first insulation layer, a bottom plate, a first patterned dielectric layer, a medium plate, a second patterned dielectric layer, and a top plate. The first patterned dielectric layer is disposed on the bottom plate. The medium plate is disposed on the first patterned dielectric layer. At least a part of the first patterned dielectric layer and the medium plate and a part of the bottom plate are disposed in a first trench penetrating the first insulation layer. The bottom plate, the first patterned dielectric layer, and the medium plate constitute a first metal-insulator-metal (MIM) capacitor. The second patterned dielectric layer is disposed on the medium plate. The top plate is disposed on the second patterned dielectric layer. The medium plate, the second patterned dielectric layer, and the top plate constitute a second MIM capacitor. The bottom plate is electrically connected with the top plate.