MIM Capacitor and Thin Film Resistor Shared Material Integration
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Solution Overview
Problem
The semiconductor industry faces high manufacturing costs and complexity in forming metal-insulator-metal (MIM) capacitors and thin film resistors in the back end of line (BEOL) portion of integrated circuit (IC) chips due to the need for multiple photolithographic processes and mask usage.
Innovation Solution
A semiconductor device is designed with a MIM capacitor and a thin film resistor where the conductive film and resistive metallic film share the same material, with specific layering and positioning to avoid electrical shorts and enhance capacitance density, using a method that includes forming dielectric layers and conductive layers in inter-metal regions with interconnect vias for electrical connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple photolithographic processes and masks are used to form MIM capacitors and thin film resistors, then manufacturing precision can be maintained, but manufacturing cost and process complexity increase significantly
Solution Approach 1:
The patent combines the formation of MIM capacitors and thin film resistors into a unified process flow. The same photolithographic steps and masks used for forming interconnect structures are also used to define the capacitor and resistor patterns, merging multiple component formation processes into one integrated sequence rather than using separate processes for each component type.
Solution Approach 2:
The patent makes the interconnect formation processes serve multiple functions: they simultaneously create the wiring structures and define the patterns for passive components (capacitors and resistors). The same masks and photolithographic steps that pattern the metal interconnects also pattern the dielectric layers to form the passive components, giving universal utility to the existing process steps.
2Reliability
If separate processes are used for forming capacitors and resistors, then component performance can be optimized, but manufacturing cost increases
Solution Approach 1:
The patent merges the manufacturing processes for capacitors and resistors by using the same deposition, photolithography, and etching sequences to form both component types. This consolidation reduces the total number of process steps and material deposits required, lowering manufacturing costs while maintaining the ability to form both component types in the same BEOL layer.
Solution Approach 2:
The patent uses uniform process conditions and material deposition parameters for forming both capacitor and resistor structures. The same dielectric materials and conductive layers are deposited with consistent thickness and composition across different device regions, ensuring homogeneous manufacturing quality while reducing process variability and cost.
3Quantity of substance
If capacitance density is increased through additional layers, then device performance improves, but process complexity and manufacturing cost increase
Solution Approach 1:
The patent makes the intermediate conductive layers and dielectric structures serve dual purposes: they function as both interconnect elements and as part of the capacitor structure. The same metal layers and dielectric deposits that form the wiring infrastructure also constitute the capacitor electrodes and insulation, achieving high capacitance density without adding separate dedicated capacitor formation steps.
Solution Approach 2:
The patent combines the interconnect stack and capacitor stack into a single integrated structure. The metal layers, dielectric layers, and via structures that form the signal routing network are simultaneously used to form the capacitor, merging two functional systems into one unified layer structure that achieves high capacitance density without increasing overall process complexity.
Data Source
AI summary
The present disclosure generally relates to a semiconductor device having a capacitor and a resistor and a method of forming the same. More particularly, the present disclosure relates to a metal-insulator-metal (MIM) capacitor and a thin film resistor (TFR) formed in a back end of line portion of an integrated circuit (IC) chip.