Wafer-Level Chip-Scale Package Common Drain Electrode
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Solution Overview
Problem
Wafer-level chip-scale packages (WLCSPs) face challenges in minimizing size due to high electric resistance from wire bonding and thick silicon semiconductor substrates, which hinder miniaturization and increase production costs.
Innovation Solution
The solution involves reducing the thickness of the semiconductor substrate by polishing the bottom part and forming a common drain electrode with a metal layer, specifically using copper or silver for the first metal layer and nickel for the second layer, to create a low-resistance current path and prevent oxidation, while maintaining visibility for laser markings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If wire bonding is used for connection between semiconductor substrate and lead frame, then electrical connection is achieved, but electric resistance increases resulting in high on-resistance
Solution Approach 1:
The patent removes the wire bonding component from the electrical connection path and replaces it with a direct metal pad-to-metal pad connection through the semiconductor substrate, eliminating the source of high resistance
Solution Approach 2:
The patent introduces a common drain electrode as an intermediary element that provides a low-resistance electrical pathway between the first and second semiconductor devices, replacing the high-resistance wire bonding method
2Strength
If thick silicon semiconductor substrate is used, then mechanical strength is improved, but package size increases preventing miniaturization
Solution Approach 1:
The patent changes the thickness parameter of the semiconductor substrate to an optimized value that provides sufficient mechanical strength while minimizing package size, and compensates for the reduced thickness through structural design
Solution Approach 2:
The patent employs a composite structure combining the semiconductor substrate with metal layers (copper or silver for first metal layer, nickel for second layer) to achieve both mechanical strength and electrical conductivity without requiring excessive substrate thickness
3Reliability
If copper or silver metal layer is deposited, then electrical conductivity is improved, but oxidation resistance is reduced
Solution Approach 1:
The patent creates a composite metal structure where copper or silver layers provide high electrical conductivity while nickel layers provide oxidation resistance, combining the advantages of different materials
Solution Approach 2:
The nickel layer acts as a protective intermediary between the copper or silver metal layer and the external environment, preventing oxidation of the conductive metal while allowing electrical function to persist
4Reliability
If multiple metal layers are formed, then electrical performance is improved, but manufacturing complexity increases
Solution Approach 1:
The patent designs the metal layers to serve multiple functions simultaneously: the copper or silver layer provides electrical conductivity while the nickel layer provides both structural support and oxidation protection, reducing the need for additional specialized layers
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces on-resistance, minimizes package thickness, and enhances power-saving capabilities, enabling the production of compact, high-performance WLCSPs with reduced warpage and handling damage, suitable for various power semiconductor modules and multi-chip packages.
Implementation Method 1
the first source metal bump, the common drain electrode, and the second source metal bump form a current path in an order of the first source metal bump, the common drain electrode, and the second source metal bump
Implementation Method 2
forming a common drain electrode with a metal layer, specifically using copper or silver for the first metal layer and nickel for the second layer, to create a low-resistance current path and prevent oxidation
Data Source
AI summary
A wafer-level chip-scale package includes: a power semiconductor comprising a first semiconductor device formed on a semiconductor substrate, and a second semiconductor device formed on the semiconductor substrate; a common drain electrode connected to the first semiconductor device and the second semiconductor device; a first source metal bump formed on a surface of the first semiconductor device; and a second source metal bump formed on the surface of the second semiconductor device; wherein the first source metal bump, the common drain electrode, and the second source metal bump form a current path in an order of the first source metal bump, the common drain electrode, and the second source metal bump.