MOS Silicide Regions with Composite Metal Layers
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Solution Overview
Problem
Conventional silicidation processes in MOS devices face challenges such as increased parasitic resistance due to scaling, with nickel silicide being sensitive to high temperatures and cobalt silicide experiencing significant resistivity roll-off at small dimensions, limiting their effectiveness in advanced technologies.
Innovation Solution
The formation of semiconductor devices with source/drain and gate silicide regions having different metal compositions, where the source/drain silicide region has a higher resistivity roll-off dimension than the gate silicide region, achieved through a method involving multiple annealing steps and distinct metallic layers to optimize silicide formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If nickel silicide is used to reduce contact resistance, then low resistivity is achieved, but the silicide becomes sensitive to high temperatures of subsequent processes
Solution Approach 1:
The patent uses a composite silicide structure with multiple metal layers (e.g., cobalt and nickel layers) to combine the advantages of different materials. The cobalt silicide provides thermal stability while the nickel silicide contributes low resistivity, resolving the contradiction between temperature sensitivity and contact resistance.
Solution Approach 2:
Different metal layers are applied to different regions or depths within the silicide structure. The patent forms a multi-layered silicide where each layer serves a specific function - some layers provide thermal stability while others provide low resistivity, allowing local optimization of properties throughout the structure.
2Temperature
If cobalt silicide is used for thermal stability, then resistance to high temperatures is improved, but significant resistivity roll-off occurs at dimensions of 35 nm or below
Solution Approach 1:
The patent combines cobalt silicide (providing thermal stability) with nickel silicide (providing low resistivity at small dimensions) in a multi-layer structure. This composite approach maintains thermal stability while preventing resistivity roll-off in advanced technology nodes.
Solution Approach 2:
The patent modifies the composition and structure of the silicide layer by introducing multiple metal layers with different properties. By changing the material parameters (metal composition, layer thickness, annealing conditions), the patent optimizes both thermal stability and resistivity characteristics for small dimensions.
3Length of moving object
If deep-submicron scaling is implemented to reduce device size, then miniaturization is achieved, but parasitic resistance increases
Solution Approach 1:
The multi-layer silicide structure with different metal compositions provides optimized electrical properties that counteract the increased parasitic resistance associated with deep-submicron scaling. The composite structure maintains low overall resistivity despite reduced device dimensions.
Solution Approach 2:
The patent applies different metal layers at different locations within the silicide region to locally optimize properties. This allows the structure to maintain low resistivity in critical areas while accommodating the overall device scaling.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the roll-off resistivities and reliability of MOS devices, allowing for more stable and efficient silicide formation even at small dimensions, thereby enhancing the performance and reliability of integrated circuits.
Implementation Method 1
The wafer is then subjected to one or more annealing steps, for example at a temperature of 700° C. or higher. This annealing process causes the metal to selectively react with the exposed silicon of the source/drain regions and the gate electrodes, thereby forming a metal silicide.
Implementation Method 2
The wafer is then subjected to one or more annealing steps, for example at a temperature of 700° C. or higher.
Data Source
AI summary
A semiconductor device with improved roll-off resistivity and reliability are provided. The semiconductor device includes a gate dielectric overlying a semiconductor substrate, a gate electrode overlying the gate dielectric, a gate silicide region on the gate electrode, a source/drain region adjacent the gate dielectric, and a source/drain silicide region on the source/drain region, wherein the source/drain silicide region and the gate silicide region have different metal compositions.