Backside Self-Aligned Via Formation for 3D Transistor Scaling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As microelectronic devices continue to shrink, the challenge of achieving higher device density through vertical scaling in three-dimensional integration is hindered by the difficulty in forming efficient self-aligned via structures that enable interconnects both above and below transistor layers without increasing the transistor footprint.
Innovation Solution
The method involves forming a trench in the source/drain region of a transistor, filling it with a material, and creating self-aligned contacts on both sides of the fill material, allowing for electrical connections between interconnect layers above and below the transistor layer within the same footprint, using techniques such as epitaxial deposition and dielectric material formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional via formation methods are used, then interconnect connections can be established, but the transistor footprint increases
Solution Approach 1:
The patent implements self-aligned vias that extend vertically through the transistor layer from both front and back sides, utilizing the third dimension (depth) to establish interconnect paths. This vertical through-silicon via approach allows connections to be made without expanding the horizontal footprint of the transistor, effectively moving the connection strategy from a 2D plane to a 3D structure.
Solution Approach 2:
The via structures are formed to be self-aligned with the transistor regions, where the via placement is automatically determined by the transistor geometry itself. This self-alignment mechanism eliminates the need for additional alignment steps and ensures that vias are precisely positioned to connect to transistor terminals without requiring extra lateral space.
2Productivity
If vertical scaling is implemented to increase device density, then more devices can be integrated, but forming efficient self-aligned via structures becomes more difficult
Solution Approach 1:
The methodology performs preliminary actions by forming sacrificial mandrels and defining via regions before the actual via etching and filling processes. The self-aligned nature of the via formation is established in advance through the transistor structure geometry, which automatically defines the via locations and dimensions, simplifying subsequent manufacturing steps even as device dimensions scale down.
Solution Approach 2:
The via formation process is segmented into distinct sequential steps: forming sacrificial mandrels, defining via regions, etching vias, and filling with conductive material. This segmentation allows each step to be optimized independently and enables precise control over via dimensions and alignment, which is critical for maintaining manufacturability as device sizes decrease.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables novel routing and scaling options by allowing electrical connections between interconnect layers without increasing the transistor footprint, providing the necessary depth for connections to other sides of the device layer without electrically connecting the transistor channel region.
Implementation Method 1
filling it with a material, and creating self-aligned contacts on both sides of the fill material
Data Source
AI summary
Methods and structures formed thereby are described, of forming self-aligned contact structures for microelectronic devices. An embodiment includes forming a trench in a source/drain region of a transistor device disposed in a device layer, wherein the device layer is on a substrate, forming a fill material in the trench, forming a source/drain material on the fill material, forming a first source/drain contact on a first side of the source/drain material, and then forming a second source drain contact on a second side of the source/drain material.