Split Gate Flash Memory Cell Array Size Reduction
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Solution Overview
Problem
As device geometries shrink, it becomes challenging to control the gap between STI oxide lines in split gate non-volatile flash memory cells, leading to excessive space usage by source and erase gate lines due to line-end rounding and difficulty in achieving precise critical dimensions.
Innovation Solution
A two-masking step process is employed to etch silicon nitride layers and form silicon trenches, allowing for right-angle STI corners and reducing the space between control gates, thereby minimizing memory cell array size by using implants to extend the source line diffusion underneath continuous isolation regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional single mask STI formation is used, then the process is simple, but STI line-end rounding occurs and critical dimension control deteriorates
Solution Approach 1:
The patent divides the STI formation process into two separate masking steps: first forming isolation regions, then forming source lines. This segmentation eliminates line-end rounding by creating right-angle corners through sequential etching operations, thereby improving critical dimension control while maintaining manufacturing feasibility
Solution Approach 2:
The patent performs preliminary formation of isolation regions with right-angle corners before forming source lines. This preliminary action establishes precise geometric boundaries that prevent subsequent line-end rounding issues and enable better critical dimension control in the final structure
2Area of moving object
If the gap between STI oxide lines is reduced to shrink cell size, then device density improves, but control over the gap becomes difficult
Solution Approach 1:
By separating the formation of isolation regions and source lines into distinct masking steps, the patent enables independent optimization of each feature's dimensions. This allows precise control of the gap between STI oxide lines while minimizing the overall memory cell area
Solution Approach 2:
The patent transitions from a single-planar masking approach to a multi-step process that effectively adds a temporal dimension to the fabrication sequence. This enables precise control of gap dimensions by controlling the timing and sequence of etching operations rather than relying solely on spatial mask design
3Manufacturing precision
If excessive space is allocated for source and erase gate lines to ensure workable gap G, then gap control becomes easier, but memory cell array size increases
Solution Approach 1:
The patent segments the formation process to create right-angle STI corners that eliminate line-end rounding, allowing the source lines to be positioned closer together without compromising gap control. This reduces the memory cell array area while maintaining manufacturable gap dimensions
Solution Approach 2:
The patent changes the geometric parameters of the STI structure by forming right-angle corners instead of rounded ends. This parameter change allows for reduced spacing between source lines and erase gates, thereby reducing the overall memory cell array area while maintaining adequate gap control
Data Source
Figure 1
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Figure 3A~4A
AI summary
A reduced size non-volatile memory cell array is achieved by forming first trenches in an insulation layer in the row direction, filling the first trenches with insulation material, forming second trenches in the insulation layer in the column direction, forming the STI isolation material in the second trenches, and forming the source regions through the first trenches. Alternately, the STI isolation regions can be made continuous, and the source diffusion implant has sufficient energy to form continuous source line diffusions that each extend across the active regions and under the STI isolation regions. This allows control gates of adjacent memory cell pairs to be formed closer together.