Semiconductor Fin Isolation via Well Trapping Layer
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Solution Overview
Problem
Semiconductor devices on bulk semiconductor substrates face leakage currents between semiconductor fins and the underlying substrate, and using semiconductor-on-insulator substrates is not compatible with stress-generating embedded materials that enhance transistor channel strain.
Innovation Solution
A well trapping layer with a doped semiconductor material is formed on the bulk semiconductor substrate, limiting dopant diffusion, and a device semiconductor material layer is epitaxially grown on top, allowing for the formation of semiconductor fins that are electrically isolated from the substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a semiconductor-on-insulator (SOI) substrate is used to provide electrical isolation of semiconductor fins from the substrate, then leakage currents are reduced, but compatibility with stress-generating embedded semiconductor materials is lost and additional processing steps are required
Solution Approach 1:
The patent introduces an intermediate well trapping layer made of doped semiconductor material between the bulk semiconductor substrate and the device semiconductor material layer. This intermediate layer acts as a mediator that provides electrical isolation functionality similar to SOI substrates while maintaining compatibility with stress-generating embedded materials in the bulk substrate, thereby resolving the contradiction between electrical isolation and material compatibility
Solution Approach 2:
The well trapping layer is selectively formed only in regions where electrical isolation is needed, rather than using a global SOI substrate structure. This localized approach allows the bulk substrate to retain its stress-generating embedded materials in other regions, achieving electrical isolation where required while preserving the benefits of stress-generating materials elsewhere
2Reliability
If a dielectric material is inserted underneath a semiconductor fin to provide electrical isolation, then leakage paths are blocked, but additional processing steps are required and total processing time increases
Solution Approach 1:
The well trapping layer is formed by doping an existing semiconductor material layer rather than inserting a separate dielectric material layer. This merging of the isolation function into the semiconductor material formation process itself eliminates the need for additional dielectric deposition and processing steps, thereby reducing processing time while achieving the same electrical isolation effect
Solution Approach 2:
The patent changes the electrical properties of the semiconductor material layer by introducing dopants to create the well trapping layer. This parameter change (adding dopants) transforms a conductive semiconductor layer into an isolating well trapping layer, achieving electrical isolation through material property modification rather than through additional structural layers, thus reducing processing complexity and time
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces leakage currents and maintains compatibility with stress-generating materials, enhancing the performance of semiconductor devices while minimizing additional processing steps.
Implementation Method 1
The dopant of the first conductivity type has a lesser diffusivity in the second semiconductor material than in the first semiconductor material or in the third semiconductor material
Implementation Method 2
A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer
Data Source
AI summary
A bulk semiconductor substrate including a first semiconductor material is provided. A well trapping layer including a second semiconductor material and a dopant is formed on a top surface of the bulk semiconductor substrate. The combination of the second semiconductor material and the dopant within the well trapping layer is selected such that diffusion of the dopant is limited within the well trapping layer. A device semiconductor material layer including a third semiconductor material can be epitaxially grown on the top surface of the well trapping layer. The device semiconductor material layer, the well trapping layer, and an upper portion of the bulk semiconductor substrate are patterned to form at least one semiconductor fin. Semiconductor devices formed in each semiconductor fin can be electrically isolated from the bulk semiconductor substrate by the remaining portions of the well trapping layer.