FS-IGBT Field Stop Layer Formation Using Thick Substrate Grinding
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Solution Overview
Problem
The manufacturing of field stop insulated gate bipolar transistors (FS-IGBTs) requires thin wafers, making them fragile and prone to warping or breakage during ion implantation and diffusion processes, limiting the use of thicker substrates and introducing N-type FS layers between P collector and N− drift regions.
Innovation Solution
A method involving the use of a thicker CZ substrate with an epitaxial layer, where the initial substrate is processed to create a thick field stop region, and then an epitaxial layer is grown with a drift region, base, and emitter, allowing for the reduction of the field stop region thickness through grinding or chemical removal, enabling the formation of a stable N-type FS layer between the P collector and N− drift layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a thin wafer is used to manufacture FS-IGBT, then the FS layer can be formed by ion implantation or diffusion, but the wafer becomes fragile and prone to warping or breakage during processing
Solution Approach 1:
The patent applies preliminary action by forming the FS layer from a thick substrate before thinning the wafer. The FS layer is created in the thick substrate using ion implantation or diffusion, ensuring proper formation and stability, and then the substrate is thinned to the final thickness after the FS layer is already in place. This sequence resolves the contradiction by performing the delicate FS layer formation when the substrate is still mechanically robust.
Solution Approach 2:
The patent inverts the conventional sequence by first forming the FS layer in a thick substrate and then thinning the substrate, rather than forming the FS layer in a thin wafer. This inversion allows the substrate to maintain mechanical strength during the ion implantation or diffusion process, preventing warping and breakage while still achieving the required thin final thickness.
2Manufacturing precision
If ion implantation or diffusion is used to form the FS layer, then the FS-IGBT structure is achieved, but a high-energy ion implantation process or wafer thinning process is required before FS layer formation
Solution Approach 1:
The patent applies preliminary action by performing the high-energy ion implantation or diffusion process to form the FS layer while the substrate is still thick and mechanically stable. This preliminary formation of the FS layer in the thick substrate eliminates the need for complex sequential thinning and re-doping processes, reducing overall process complexity while maintaining doping precision.
3Reliability
If a thick substrate is used during manufacturing, then wafer warping and breakage are avoided, but the FS layer cannot be properly formed by conventional ion implantation or diffusion processes
Solution Approach 1:
The patent resolves this contradiction by performing the FS layer formation as a preliminary action in the thick substrate. The ion implantation or diffusion process is applied to the thick substrate to create the FS layer, ensuring both structural stability during processing and proper FS layer formation. After the FS layer is established, the substrate is then thinned to the final thickness, maintaining both reliability and manufacturing precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the use of thicker, more rugged wafers, reducing the risk of warping and breakage, and enables the control of operational characteristics by setting the FS region thickness, resulting in improved stability and performance of the FS-IGBT with reduced saturation collector voltage and turn-off loss.
Implementation Method 1
The CZ substrate is processed by ion implantation and diffusion to create a thick, initial field stop (FS) region doped with a first polarity dopant
Implementation Method 2
The CZ substrate is processed by ion implantation and diffusion to create a thick, initial field stop (FS) region doped with a first polarity dopant
Implementation Method 3
That substrate is then processed to grow an epitaxial layer
Implementation Method 4
The epitaxial layer is doped by ion implanting and diffusion to create a drift region
Implementation Method 5
The epitaxial layer is doped by ion implanting and diffusion to create a drift region
Implementation Method 6
The surface of the epitaxial region is doped by ion implantation and diffusion to form first a base region of opposite polarity and then, in the base region, an emitter region
Implementation Method 7
The surface of the epitaxial region is doped by ion implantation and diffusion to form first a base region of opposite polarity and then, in the base region, an emitter region
Data Source
AI summary
Provided are a power semiconductor device using a silicon substrate as a FS layer and a method of manufacturing the same. A semiconductor substrate of a first conductivity type is prepared. An epitaxial layer is grown on one surface of the semiconductor substrate. Here, the epitaxial layer is doped at a concentration lower than that of the semiconductor substrate and is intended to be used as a drift region. A base region of a second conductivity type is formed in a predetermined region of the epitaxial layer. An emitter region of the first conductivity type is formed in a predetermined region of the base region. A gate electrode with a gate insulating layer is formed on the base region between the emitter region and the drift region of the epitaxial layer. A rear surface of the semiconductor substrate is ground to reduce the thickness of the semiconductor substrate, thereby setting an FS region of the first conductivity type. A collector region of the second conductivity type is formed on the ground surface of the semiconductor substrate of the FS region, thereby forming an FS-IGBT.