Vertical Non-Volatile Memory Air Gaps Reduce Parasitic Capacitance
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Solution Overview
Problem
Current non-volatile memory devices face challenges in increasing integration density and signal transmission reliability due to limitations in their planar transistor structures, which hinder the ability to efficiently store and process large amounts of data in reduced volumes.
Innovation Solution
A vertical structure non-volatile memory device is designed with semiconductor regions extending vertically on a substrate, featuring memory cell strings with multiple transistors and insulating air gaps between adjacent strings, enhancing signal transmission and reducing parasitic capacitance through the use of gate dielectric layers and connection electrodes that connect transistors in series.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If planar transistor structure is used, then manufacturing process is simple, but integration density cannot be increased
Solution Approach 1:
The patent transitions from a planar (2D) transistor structure to a vertical (3D) transistor structure by extending the channel, gate electrode, and gate dielectric layer vertically from the substrate surface. This dimensional change allows multiple memory cell strings to be stacked above the substrate, dramatically increasing integration density while maintaining manufacturing feasibility through adapted fabrication processes
2Quantity of substance
If memory cell strings are placed adjacent to each other to increase integration, then integration density increases, but parasitic capacitance increases causing signal transmission issues
Solution Approach 1:
The patent introduces air gaps as intermediary regions positioned between adjacent memory cell strings. These air gaps act as electrical isolators that reduce parasitic capacitance coupling between neighboring strings, thereby improving signal transmission reliability while allowing the strings to remain closely spaced for high integration density
Solution Approach 2:
The air gaps are strategically positioned only in specific regions where parasitic capacitance would be problematic, namely between adjacent memory cell strings. This localized application of insulation maintains the overall compact structure while targeting the specific areas that cause signal transmission issues
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The vertical structure improves signal transmission reliability and reduces RC delay, allowing for increased integration density and efficient data storage in a compact form, thereby addressing the limitations of traditional planar structures.
Implementation Method 1
insulating regions that are formed as air gaps between the first selection transistors of the adjacent memory cell strings
Data Source
AI summary
A vertical structure non-volatile memory device includes semiconductor regions that vertically extend on a substrate, a plurality of memory cell strings that vertically extend on the substrate along sidewalls of the semiconductor regions and include a plurality of memory cells and at least one or more first selection transistors, which are disposed on sides of the memory cells and are adjacent to one another. A plurality of wordlines is connected to the memory cells of the memory cell strings. A first selection line is connected to the selection transistors of the memory cell strings and insulating regions are formed as air gaps between the first selection transistors of the adjacent memory cell strings.