Nanosheet Transistor Integration via Sacrificial Layer Oxidation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor fabrication processes face challenges in integrating silicon channel n-type and silicon germanium channel p-type field effect transistors on the same substrate due to differences in etching chemistries and gate stack architectures required for nFET and pFET devices, leading to difficulties in controlling punch-through leakage currents and achieving desired device performance.
Innovation Solution
A method is developed to form vertically stacked and isolated n-type and p-type nanosheet/nanowire transistors by creating a sacrificial nanosheet layer with a greater thickness than the alternating nanosheets, allowing for selective etching to open insulation regions and convert them into dielectric oxide for isolation, enabling the integration of nFET and pFET channels on the same substrate with appropriate gate architectures and threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional planar FET fabrication processes are used to integrate nFET and pFET on the same substrate, then manufacturing simplicity is maintained, but device density and performance are limited due to inability to achieve fuller depletion and reduced short-channel effects
Solution Approach 1:
The patent transitions from planar 2D transistor architecture to vertically stacked 3D nanosheet architecture. Multiple nanosheet channels are stacked vertically to form a columnar structure, enabling fuller gate control around the channel perimeter. This dimensional change increases device density without sacrificing performance and allows nFET and pFET integration on the same substrate through selective sacrificial layer removal.
Solution Approach 2:
The channel region is segmented into multiple thin nanosheet layers stacked vertically, with each nanosheet providing a controlled conduction path. The gate wraps around each nanosheet individually, creating multiple independent channels that can be selectively activated. This segmentation enables better electrostatic control and reduced short-channel effects compared to a single thick planar channel.
2Reliability
If different etching chemistries are used for nFET and pFET fabrication, then device-specific performance requirements are met, but process complexity increases and integration on the same substrate becomes difficult
Solution Approach 1:
The patent employs different sacrificial materials (silicon vs. silicon germanium) in different spatial regions of the same substrate. nFET regions use silicon sacrificial layers that can be selectively removed with specific etchants, while pFET regions use silicon germanium sacrificial layers removable with different etchants. This local differentiation allows device-specific optimization while maintaining overall process integration.
Solution Approach 2:
Sacrificial nanosheet layers are pre-formed during the epitaxial growth process before final device fabrication. These sacrificial layers are strategically positioned and differentiated by material composition in advance, enabling subsequent selective removal to create isolated nFET and pFET regions. This preliminary action simplifies the overall integration process by establishing region-specific characteristics early in fabrication.
3Manufacturing precision
If thicker sacrificial nanosheet layers are used to enable selective etching, then insulation region opening is achieved, but control over etching selectivity and prevention of damage to channel nanosheets becomes more challenging
Solution Approach 1:
The patent creates asymmetric thickness distribution among sacrificial nanosheet layers. Specific sacrificial layers are made thicker than others to serve as etch-stop layers or to enable selective removal. This asymmetric design allows the etching process to selectively remove certain sacrificial layers while leaving others intact, providing precise control over insulation region formation without compromising channel nanosheet integrity.
Solution Approach 2:
The patent varies the thickness parameter of sacrificial nanosheet layers to control etching behavior. By adjusting the thickness of specific sacrificial layers relative to channel nanosheets, the process achieves selective removal of sacrificial material while preserving channel structures. This parameter control enables precise definition of insulation regions while maintaining channel nanosheet integrity through careful etch selectivity management.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively addresses punch-through leakage issues and allows for the co-integration of nFET and pFET channels on a single substrate, providing enhanced device performance and scalability down to 7-nanometer technology and beyond.
Implementation Method 1
opening the insulation region by applying an etchant to the exposed surface area of the first sacrificial nanosheet, the exposed surface areas of the alternating channel nanosheets, and the exposed surface areas of the alternating sacrificial stack nanosheets, wherein the etchant is configured to include an etchant selectivity, wherein the etchant selectivity is based at least in part on the type of material to which the etchant is applied
Implementation Method 2
converting them into dielectric oxide for isolation, enabling the integration of nFET and pFET channels on the same substrate
Data Source
AI summary
Embodiments of the invention are directed to a method of forming an insulation region during fabrication of a nanosheet channel field effect transistor (FET). The method includes forming a first sacrificial nanosheet across from a major surface of a substrate, wherein the first sacrificial nanosheet includes a first semiconductor material at a concentration percentage less than or equal to about fifty percent. A first nanosheet stack is formed on an opposite side of the first sacrificial nanosheet from the major surface of the substrate, wherein the first nanosheet stack includes alternating channel nanosheets and sacrificial stack nanosheets, wherein a thickness dimension of the first sacrificial nanosheet is greater than a thickness dimension of at least one of the alternating channel nanosheets. An oxidation operation is performed that converts the first sacrificial nanosheet to a dielectric oxide, wherein the insulation region includes the dielectric oxide.