Work Function Engineering for eDRAM MOSFET Gate Stacks
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Solution Overview
Problem
In embedded DRAM (eDRAM) field effect transistors (FETs), high junction leakage and voltage threshold (Vt) variability due to high channel doping are critical issues that affect retention time and subthreshold leakage, requiring innovative gate stack designs to reduce these problems.
Innovation Solution
A gate stack with a high-K dielectric layer and a metal oxide cap is used for the eDRAM array transistor to move the work function close to the valence band edge, reducing junction leakage and Vt variability, while a thin metal oxide layer is inserted between the high-K gate dielectric and metal gate for logic PFETs to modulate the work function, achieving higher Vt for array NFETs and lower Vt for logic NFETs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If high channel doping is used in eDRAM array transistors, then junction leakage is reduced, but voltage threshold (Vt) variability increases
Solution Approach 1:
The patent changes the work function parameter of the gate stack by introducing a metal oxide layer (such as aluminum oxide) between the high-K dielectric and the metal gate. This parameter change allows achieving high Vt (>0.8V) for array NFETs without relying on high channel doping, thereby reducing Vt variability while maintaining low junction leakage
Solution Approach 2:
The patent employs a composite gate stack structure consisting of multiple materials: high-K dielectric material, metal oxide material (e.g., aluminum oxide), and metal gate material (e.g., titanium nitride). This composite structure enables independent optimization of work function and channel doping, resolving the contradiction between junction leakage and Vt variability
2Object-generated harmful factors
If high channel doping is used in eDRAM array transistors, then junction leakage is reduced, but retention time decreases
Solution Approach 1:
By changing the work function parameter through the metal oxide layer insertion, the patent achieves high Vt without high channel doping. This parameter change directly improves retention time while maintaining low junction leakage, as retention time is exponentially dependent on Vt and inversely dependent on junction leakage
3Reliability
If work function is moved close to valence band edge for array NFETs, then Vt is increased, but manufacturing complexity increases
Solution Approach 1:
The patent segments the gate stack into distinct functional layers: high-K dielectric layer, metal oxide work function control layer, and metal gate layer. This segmentation allows independent optimization of each layer's properties and simplifies the manufacturing process by enabling separate deposition and control of each layer
Solution Approach 2:
The metal oxide layer serves as an intermediary between the high-K dielectric and the metal gate. This intermediary layer provides work function control without requiring direct contact between the high-K dielectric and metal gate, simplifying the overall manufacturing process while achieving the desired electrical characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces junction leakage and Vt variability, allowing for higher Vt in eDRAM array transistors without high channel doping, and modulates work functions for logic transistors, improving retention time and reducing subthreshold leakage.
Implementation Method 1
A gate stack with a high-K dielectric layer and a metal oxide cap is used for the eDRAM array transistor to move the work function close to the valence band edge, reducing junction leakage and Vt variability, while a thin metal oxide layer is inserted between the high-K gate dielectric and metal gate for logic PFETs to modulate the work function
Data Source
AI summary
Embedded DRAM MOSFETs including an array NFET having a gate stack comprising a high-K dielectric layer upon which is deposited a first metal oxide layer (CD1) then a conductive layer (TiN), and then a polysilicon layer (Poly). A logic PFET having substantially the same gate stack as the array NFET, and a logic NFET having a third gate stack comprising the high-K dielectric layer upon which is deposited the conductive layer (TiN) and then the polysilicon layer (Poly), without the first metal oxide layer (CD1) between the high-K dielectric layer and the conductive layer (TiN). The array NFET may therefore have a higher gate stack work function than the logic NFET, but substantially the same gate stack work function as the logic PFET.