Single-Dopant Accumulation Mode FET for Simplified Fabrication
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Solution Overview
Problem
Conventional field effect transistors (FETs) face challenges in achieving efficient on-state current and subthreshold slope values due to complex fabrication requirements and dependence on gate capacitance, with prior art discouraging single doping type nanowire FET structures for their performance.
Innovation Solution
A gated microelectronic device with a single dopant type across the source, channel, and drain regions, utilizing ohmic contacts separated from the channel edges to prevent ambipolar behavior, and featuring a weak dependence on gate capacitance for current-voltage behavior, allowing for simpler fabrication and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional MOSFET structures with heavily doped source and drain regions are used, then ohmic contacts are formed, but the device requires complex fabrication with multiple etching and deposition steps
Solution Approach 1:
The patent applies homogeneity by using a single doping type (either n-type or p-type) throughout the entire semiconductor channel, source, and drain regions. This eliminates the need for separate n-type and p-type doping regions, simplifying the fabrication process while maintaining reliable ohmic contacts through the uniformly doped structure.
Solution Approach 2:
The patent changes the doping parameter from the conventional approach of using different doping types in different regions to a uniform doping type throughout. By adjusting the doping concentration and maintaining single-type doping across all regions, the patent achieves simplified fabrication while preserving the necessary electrical characteristics for ohmic contacts.
2Reliability
If the insulating layer thickness is reduced to increase gate capacitance, then gate to channel coupling improves, but gate leakage current increases
Solution Approach 1:
The patent changes the operational parameter from relying on high gate capacitance through thin insulators to relying on accumulation mode operation. By operating in accumulation mode where majority carriers are accumulated at the interface, the patent achieves strong gate coupling without requiring extremely thin insulating layers, thus avoiding excessive gate leakage.
3Ease of manufacture
If single doping type nanowire FET structures are used, then fabrication is simplified, but on-state current and subthreshold slope performance deteriorates
Solution Approach 1:
The patent applies dynamics by utilizing the accumulation and depletion of majority carriers in response to gate voltage changes. The dynamic accumulation of carriers at the semiconductor-insulator interface under positive gate bias enables strong on-state current, while the dynamic depletion creates effective off-state, achieving good subthreshold slope despite single doping type.
Solution Approach 2:
The patent optimizes the doping concentration parameter to achieve the desired balance between on-state current and off-state leakage. By carefully selecting the doping concentration in the single-doped structure, the patent achieves sufficient carrier density for high on-state current while maintaining the ability to deplete carriers for low off-state current and good subthreshold slope.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The device exhibits enhanced on-state current and subthreshold slope performance with reduced dependence on gate capacitance, enabling more straightforward fabrication and integration into microelectronics, while avoiding ambipolar behavior and quantum mechanical carrier tunneling issues.
Implementation Method 1
A gate contact applies a gate voltage bias to control charge carrier accumulation and depletion in the underlying channel portion
Implementation Method 2
an ohmic contact to a source semiconductor region... an ohmic contact to a drain semiconductor region
Data Source
AI summary
A gated microelectronic device is provided that has a source with a source ohmic contact with the source characterized by a source dopant type and concentration. A drain with a drain ohmic contact with the drain characterized by a drain dopant type and concentration. An intermediate channel portion characterized by a channel portion dopant type and concentration. An insulative dielectric is in contact with the channel portion and overlaid in turn by a gate. A gate contact applies a gate voltage bias to control charge carrier accumulation and depletion in the underlying channel portion. This channel portion has a dimension normal to the gate which is fully depleted in the off-state. The dopant type is the same across the source, drain and the channel portion of the device. The device on-state current is determined by the doping and, unlike a MOSFET, is not directly proportional to device capacitance.