Air Gap Insulating Layers Reduce RC Delay in 3D Memory Word Lines
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Solution Overview
Problem
In three-dimensional nonvolatile memory devices, there is a need to improve signal speed in word lines stacked in the height direction of pillars, as existing technologies face challenges in optimizing the resistance and capacitance of these lines due to the presence of columnar structures.
Innovation Solution
The semiconductor memory device incorporates a stacked body with alternately layered conductive and insulating layers, featuring air gap layers created by thinner layers extending from the main insulating layer ends, which are separated and in contact at the slit regions, reducing interline capacitance and enhancing signal speed by forming low resistance bands along the word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If word lines are stacked in the height direction of pillars in three-dimensional nonvolatile memory, then memory capacity is increased, but signal speed in word lines deteriorates due to increased resistance and capacitance
Solution Approach 1:
Air gap layers are introduced between adjacent word lines to extract and eliminate the harmful capacitive coupling between them. By removing the dielectric material and replacing it with air (or vacuum), the interline capacitance is significantly reduced, thereby improving signal speed while maintaining the stacked three-dimensional memory structure
Solution Approach 2:
The air gap layers are selectively formed only in specific regions between word lines where capacitive coupling needs to be reduced. The insulating layer thickness is locally varied to create thinner regions that form air gaps when patterned, allowing precise control of capacitance reduction in critical areas while maintaining structural integrity elsewhere
2Speed
If insulating layer thickness is reduced to form air gap layers, then interline capacitance is reduced and signal speed is improved, but structural integrity and strength may be compromised
Solution Approach 1:
The insulating layer is designed with spatially varying thickness: thinner regions are formed specifically where air gap layers are needed between word lines to reduce capacitance, while thicker regions are maintained in areas requiring structural support. This local differentiation allows simultaneous optimization of electrical performance and mechanical strength
Solution Approach 2:
The insulating layer is segmented into multiple thickness regions within the same layer structure. By dividing the layer into thinner and thicker portions, the patent enables formation of air gaps in specific locations while preserving structural integrity in other locations, resolving the contradiction between capacitance reduction and strength maintenance
Data Source
AI summary
A semiconductor memory device according to an embodiment includes a slit-side end portion of an insulating layer includes a main body of the insulating layer, a first thin layer thinner than the main body and extending from an end portion closer to an upper surface of the main body, the end portion facing the slit, toward the slit, and a second thin layer thinner than the main body and extending from an end portion closer to a lower surface of the main body, the end portion facing the slit, toward the slit, and the insulating layer includes an air gap layer surrounded by the main body, the first thin layer, and the second thin layer in the slit-side end portion.